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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: memops.v
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// Filename: memops.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// error signal).
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// error signal).
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015,2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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module memops(i_clk, i_rst, i_stb, i_lock,
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module memops(i_clk, i_rst, i_stb, i_lock,
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i_op, i_addr, i_data, i_oreg,
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i_op, i_addr, i_data, i_oreg,
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o_busy, o_valid, o_err, o_wreg, o_result,
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o_busy, o_valid, o_err, o_wreg, o_result,
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o_wb_cyc_gbl, o_wb_cyc_lcl,
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o_wb_cyc_gbl, o_wb_cyc_lcl,
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o_wb_stb_gbl, o_wb_stb_lcl,
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o_wb_stb_gbl, o_wb_stb_lcl,
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o_wb_we, o_wb_addr, o_wb_data,
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o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
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parameter ADDRESS_WIDTH=32, IMPLEMENT_LOCK=0;
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parameter ADDRESS_WIDTH=30, IMPLEMENT_LOCK=0, WITH_LOCAL_BUS=0;
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localparam AW=ADDRESS_WIDTH;
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localparam AW=ADDRESS_WIDTH;
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input i_clk, i_rst;
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input i_clk, i_rst;
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input i_stb, i_lock;
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input i_stb, i_lock;
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// CPU interface
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// CPU interface
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input i_op;
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input [2:0] i_op;
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input [31:0] i_addr;
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input [31:0] i_addr;
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input [31:0] i_data;
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input [31:0] i_data;
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input [4:0] i_oreg;
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input [4:0] i_oreg;
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// CPU outputs
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// CPU outputs
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output wire o_busy;
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output wire o_busy;
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output wire o_wb_cyc_lcl;
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output wire o_wb_cyc_lcl;
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output reg o_wb_stb_lcl;
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output reg o_wb_stb_lcl;
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output reg o_wb_we;
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output reg o_wb_we;
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output reg [(AW-1):0] o_wb_addr;
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output reg [(AW-1):0] o_wb_addr;
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output reg [31:0] o_wb_data;
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output reg [31:0] o_wb_data;
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output reg [3:0] o_wb_sel;
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_ack, i_wb_stall, i_wb_err;
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input i_wb_ack, i_wb_stall, i_wb_err;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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reg r_wb_cyc_gbl, r_wb_cyc_lcl;
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reg r_wb_cyc_gbl, r_wb_cyc_lcl;
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wire gbl_stb, lcl_stb;
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wire gbl_stb, lcl_stb;
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assign lcl_stb = (i_stb)&&(i_addr[31:24]==8'hff);
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assign lcl_stb = (i_stb)&&(WITH_LOCAL_BUS!=0)&&(i_addr[31:24]==8'hff);
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assign gbl_stb = (i_stb)&&(i_addr[31:24]!=8'hff);
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assign gbl_stb = (i_stb)&&((WITH_LOCAL_BUS==0)||(i_addr[31:24]!=8'hff));
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initial r_wb_cyc_gbl = 1'b0;
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initial r_wb_cyc_gbl = 1'b0;
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initial r_wb_cyc_lcl = 1'b0;
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initial r_wb_cyc_lcl = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (o_wb_cyc_lcl)
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if (o_wb_cyc_lcl)
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o_wb_stb_lcl <= (o_wb_stb_lcl)&&(i_wb_stall);
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o_wb_stb_lcl <= (o_wb_stb_lcl)&&(i_wb_stall);
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else
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else
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o_wb_stb_lcl <= lcl_stb; // Grab wishbone on new operation
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o_wb_stb_lcl <= lcl_stb; // Grab wishbone on new operation
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reg [3:0] r_op;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_stb)
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if (i_stb)
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begin
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begin
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o_wb_we <= i_op;
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o_wb_we <= i_op[0];
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o_wb_data <= i_data;
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casez({ i_op[2:1], i_addr[1:0] })
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o_wb_addr <= i_addr[(AW-1):0];
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`ifdef ZERO_ON_IDLE
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4'b100?: o_wb_data <= { i_data[15:0], 16'h00 };
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4'b101?: o_wb_data <= { 16'h00, i_data[15:0] };
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4'b1100: o_wb_data <= { i_data[7:0], 24'h00 };
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4'b1101: o_wb_data <= { 8'h00, i_data[7:0], 16'h00 };
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4'b1110: o_wb_data <= { 16'h00, i_data[7:0], 8'h00 };
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4'b1111: o_wb_data <= { 24'h00, i_data[7:0] };
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`else
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4'b10??: o_wb_data <= { (2){ i_data[15:0] } };
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4'b11??: o_wb_data <= { (4){ i_data[7:0] } };
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`endif
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default: o_wb_data <= i_data;
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endcase
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o_wb_addr <= i_addr[(AW+1):2];
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`ifdef SET_SEL_ON_READ
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if (i_op[0] == 1'b0)
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o_wb_sel <= 4'hf;
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else
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`endif
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casez({ i_op[2:1], i_addr[1:0] })
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4'b01??: o_wb_sel <= 4'b1111;
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4'b100?: o_wb_sel <= 4'b1100;
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4'b101?: o_wb_sel <= 4'b0011;
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4'b1100: o_wb_sel <= 4'b1000;
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4'b1101: o_wb_sel <= 4'b0100;
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4'b1110: o_wb_sel <= 4'b0010;
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4'b1111: o_wb_sel <= 4'b0001;
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default: o_wb_sel <= 4'b1111;
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endcase
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r_op <= { i_op[2:1] , i_addr[1:0] };
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end
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`ifdef ZERO_ON_IDLE
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else if ((!o_wb_cyc_gbl)&&(!o_wb_cyc_lcl))
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begin
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o_wb_we <= 1'b0;
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o_wb_addr <= 0;
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o_wb_data <= 32'h0;
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o_wb_sel <= 4'h0;
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end
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end
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`endif
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initial o_valid = 1'b0;
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initial o_valid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_valid <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we);
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o_valid <= (!i_rst)&&((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we);
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initial o_err = 1'b0;
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initial o_err = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_err <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_err);
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o_err <= (!i_rst)&&((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_err);
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assign o_busy = (o_wb_cyc_gbl)||(o_wb_cyc_lcl);
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assign o_busy = (o_wb_cyc_gbl)||(o_wb_cyc_lcl);
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_stb)
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if (i_stb)
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o_wreg <= i_oreg;
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o_wreg <= i_oreg;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_wb_ack)
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`ifdef ZERO_ON_IDLE
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o_result <= i_wb_data;
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if (!i_wb_ack)
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o_result <= 32'h0;
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else
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`endif
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casez(r_op)
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4'b01??: o_result <= i_wb_data;
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4'b100?: o_result <= { 16'h00, i_wb_data[31:16] };
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4'b101?: o_result <= { 16'h00, i_wb_data[15: 0] };
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4'b1100: o_result <= { 24'h00, i_wb_data[31:24] };
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4'b1101: o_result <= { 24'h00, i_wb_data[23:16] };
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4'b1110: o_result <= { 24'h00, i_wb_data[15: 8] };
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4'b1111: o_result <= { 24'h00, i_wb_data[ 7: 0] };
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default: o_result <= i_wb_data;
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endcase
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generate
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generate
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if (IMPLEMENT_LOCK != 0)
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if (IMPLEMENT_LOCK != 0)
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begin
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begin
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reg lock_gbl, lock_lcl;
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reg lock_gbl, lock_lcl;
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