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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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i_stall_n, i_pc, o_i, o_pc, o_v,
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i_stall_n, i_pc, o_i, o_pc, o_v,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
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o_illegal);
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o_illegal);
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parameter LGCACHELEN = 8, ADDRESS_WIDTH=24,
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parameter LGCACHELEN = 8, ADDRESS_WIDTH=24,
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CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH,
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LGLINES=5; // Log of the number of separate cache lines
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CW=LGCACHELEN, PW=LGCACHELEN-5;
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localparam CACHELEN=(1<<LGCACHELEN); // Size of our cache memory
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localparam CW=LGCACHELEN; // Short hand for LGCACHELEN
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localparam PW=LGCACHELEN-LGLINES; // Size of a cache line
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localparam BUSW = 32; // Number of data lines on the bus
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localparam AW=ADDRESS_WIDTH; // Shorthand for ADDRESS_WIDTH
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input i_clk, i_rst, i_new_pc;
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input i_clk, i_rst, i_new_pc;
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input i_clear_cache;
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input i_clear_cache;
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input i_stall_n;
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input i_stall_n;
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input [(AW-1):0] i_pc;
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input [(AW-1):0] i_pc;
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output wire [(BUSW-1):0] o_i;
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output wire [(BUSW-1):0] o_i;
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assign o_wb_we = 1'b0;
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assign o_wb_we = 1'b0;
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assign o_wb_data = 0;
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assign o_wb_data = 0;
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wire r_v;
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wire r_v;
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reg [(BUSW-1):0] cache [0:((1<<CW)-1)];
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reg [(BUSW-1):0] cache [0:((1<<CW)-1)];
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reg [(AW-CW-1):0] tags [0:((1<<(CW-PW))-1)];
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reg [(AW-CW-1):0] tags [0:((1<<(LGLINES))-1)];
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reg [((1<<(CW-PW))-1):0] vmask;
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reg [((1<<(LGLINES))-1):0] vmask;
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reg [(AW-1):0] lastpc;
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reg [(AW-1):0] lastpc;
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reg [(CW-1):0] rdaddr;
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reg [(CW-1):0] rdaddr;
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reg [(AW-1):CW] tagvalipc, tagvallst;
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reg [(AW-1):CW] tagvalipc, tagvallst;
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wire [(AW-1):CW] tagval;
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wire [(AW-1):CW] tagval;
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// cache line would get read, and the instruction would read from the
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// cache line would get read, and the instruction would read from the
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// last cache line.
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// last cache line.
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reg svmask;
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reg svmask;
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initial vmask = 0;
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initial vmask = 0;
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initial svmask = 1'b0;
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initial svmask = 1'b0;
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reg [(CW-PW-1):0] saddr;
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reg [(LGLINES-1):0] saddr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(i_clear_cache))
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if ((i_rst)||(i_clear_cache))
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begin
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begin
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vmask <= 0;
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vmask <= 0;
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svmask<= 1'b0;
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svmask<= 1'b0;
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