URL
https://opencores.org/ocsvn/openarty/openarty/trunk
[/] [openarty/] [trunk/] [rtl/] [cpu/] [pipemem.v] - Diff between revs 3 and 32
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 3 |
Rev 32 |
| Line 50... |
Line 50... |
input [31:0] i_addr;
|
input [31:0] i_addr;
|
input [31:0] i_data;
|
input [31:0] i_data;
|
input [4:0] i_oreg;
|
input [4:0] i_oreg;
|
// CPU outputs
|
// CPU outputs
|
output wire o_busy;
|
output wire o_busy;
|
output reg o_pipe_stalled;
|
output wire o_pipe_stalled;
|
output reg o_valid;
|
output reg o_valid;
|
output reg o_err;
|
output reg o_err;
|
output reg [4:0] o_wreg;
|
output reg [4:0] o_wreg;
|
output reg [31:0] o_result;
|
output reg [31:0] o_result;
|
// Wishbone outputs
|
// Wishbone outputs
|
| Line 162... |
Line 162... |
always @(posedge i_clk)
|
always @(posedge i_clk)
|
// if (i_wb_ack) isn't necessary, since o_valid won't be true
|
// if (i_wb_ack) isn't necessary, since o_valid won't be true
|
// then either.
|
// then either.
|
o_result <= i_wb_data;
|
o_result <= i_wb_data;
|
|
|
/*
|
assign o_pipe_stalled = (cyc)
|
assign o_pipe_stalled = (cyc)
|
&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
|
&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
|
|
*/
|
|
always @(posedge i_clk)
|
|
o_pipe_stalled <= (i_pipe_stb)&&(cyc)&&(i_wb_stall);
|
|
|
|
|
|
generate
|
generate
|
if (IMPLEMENT_LOCK != 0)
|
if (IMPLEMENT_LOCK != 0)
|
begin
|
begin
|
reg lock_gbl, lock_lcl;
|
reg lock_gbl, lock_lcl;
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.