| Line 40... |
Line 40... |
o_busy, o_pipe_stalled, o_valid, o_err, o_wreg, o_result,
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o_busy, o_pipe_stalled, o_valid, o_err, o_wreg, o_result,
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o_wb_cyc_gbl, o_wb_cyc_lcl,
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o_wb_cyc_gbl, o_wb_cyc_lcl,
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o_wb_stb_gbl, o_wb_stb_lcl,
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o_wb_stb_gbl, o_wb_stb_lcl,
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o_wb_we, o_wb_addr, o_wb_data,
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o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
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parameter ADDRESS_WIDTH=32, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH;
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parameter ADDRESS_WIDTH=32, IMPLEMENT_LOCK=0;
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localparam AW=ADDRESS_WIDTH;
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input i_clk, i_rst;
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input i_clk, i_rst;
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input i_pipe_stb, i_lock;
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input i_pipe_stb, i_lock;
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// CPU interface
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// CPU interface
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input i_op;
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input i_op;
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input [31:0] i_addr;
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input [31:0] i_addr;
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| Line 88... |
Line 89... |
else if ((i_wb_ack)&&(cyc))
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else if ((i_wb_ack)&&(cyc))
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rdaddr <= rdaddr + 4'h1;
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rdaddr <= rdaddr + 4'h1;
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assign nxt_rdaddr = rdaddr + 4'h1;
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assign nxt_rdaddr = rdaddr + 4'h1;
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|
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wire gbl_stb, lcl_stb;
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wire gbl_stb, lcl_stb;
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assign lcl_stb = (i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
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assign lcl_stb = (i_addr[31:24]==8'hff);
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assign gbl_stb = (~lcl_stb);
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assign gbl_stb = (~lcl_stb);
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//= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
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//= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
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initial cyc = 0;
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initial cyc = 0;
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initial r_wb_cyc_lcl = 0;
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initial r_wb_cyc_lcl = 0;
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