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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbdblpriarb.v
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// Filename: wbdblpriarb.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015,2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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module wbdblpriarb(i_clk, i_rst,
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module wbdblpriarb(i_clk, i_rst,
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// Bus A
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// Bus A
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i_a_cyc_a,i_a_cyc_b,i_a_stb_a,i_a_stb_b,i_a_we,i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err,
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i_a_cyc_a,i_a_cyc_b,i_a_stb_a,i_a_stb_b,i_a_we,i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err,
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// Bus B
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// Bus B
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i_b_cyc_a,i_b_cyc_b,i_b_stb_a,i_b_stb_b,i_b_we,i_b_adr, i_b_dat, o_b_ack, o_b_stall, o_b_err,
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i_b_cyc_a,i_b_cyc_b,i_b_stb_a,i_b_stb_b,i_b_we,i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err,
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// Both buses
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// Both buses
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o_cyc_a, o_cyc_b, o_stb_a, o_stb_b, o_we, o_adr, o_dat,
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o_cyc_a, o_cyc_b, o_stb_a, o_stb_b, o_we, o_adr, o_dat, o_sel,
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i_ack, i_stall, i_err);
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i_ack, i_stall, i_err);
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parameter DW=32, AW=32;
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parameter DW=32, AW=32;
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// Wishbone doesn't use an i_ce signal. While it could, they dislike
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// Wishbone doesn't use an i_ce signal. While it could, they dislike
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// what it would (might) do to the synchronous reset signal, i_rst.
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// what it would (might) do to the synchronous reset signal, i_rst.
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input i_clk, i_rst;
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input i_clk, i_rst;
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// Bus A
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// Bus A
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input i_a_cyc_a, i_a_cyc_b, i_a_stb_a, i_a_stb_b, i_a_we;
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input i_a_cyc_a, i_a_cyc_b, i_a_stb_a, i_a_stb_b, i_a_we;
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input [(AW-1):0] i_a_adr;
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input [(AW-1):0] i_a_adr;
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input [(DW-1):0] i_a_dat;
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input [(DW-1):0] i_a_dat;
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input [(DW/8-1):0] i_a_sel;
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output wire o_a_ack, o_a_stall, o_a_err;
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output wire o_a_ack, o_a_stall, o_a_err;
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// Bus B
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// Bus B
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input i_b_cyc_a, i_b_cyc_b, i_b_stb_a, i_b_stb_b, i_b_we;
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input i_b_cyc_a, i_b_cyc_b, i_b_stb_a, i_b_stb_b, i_b_we;
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input [(AW-1):0] i_b_adr;
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input [(AW-1):0] i_b_adr;
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input [(DW-1):0] i_b_dat;
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input [(DW-1):0] i_b_dat;
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input [(DW/8-1):0] i_b_sel;
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output wire o_b_ack, o_b_stall, o_b_err;
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output wire o_b_ack, o_b_stall, o_b_err;
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//
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//
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output wire o_cyc_a,o_cyc_b, o_stb_a, o_stb_b, o_we;
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output wire o_cyc_a,o_cyc_b, o_stb_a, o_stb_b, o_we;
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output wire [(AW-1):0] o_adr;
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output wire [(AW-1):0] o_adr;
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output wire [(DW-1):0] o_dat;
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output wire [(DW-1):0] o_dat;
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output wire [(DW/8-1):0] o_sel;
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input i_ack, i_stall, i_err;
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input i_ack, i_stall, i_err;
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// All of our logic is really captured in the 'r_a_owner' register.
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// All of our logic is really captured in the 'r_a_owner' register.
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// This register determines who owns the bus. If no one is requesting
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// This register determines who owns the bus. If no one is requesting
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// the bus, ownership goes to A on the next clock. Otherwise, if B is
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// the bus, ownership goes to A on the next clock. Otherwise, if B is
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// requesting the bus and A is not, then ownership goes to not A on
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// requesting the bus and A is not, then ownership goes to not A on
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// the next clock. (Sounds simple ...)
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// the next clock. (Sounds simple ...)
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//
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//
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// The CYC logic is here to make certain that, by the time we determine
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// The CYC logic is here to make certain that, by the time we determine
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// who the bus owner is, we can do so based upon determined criteria.
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// who the bus owner is, we can do so based upon determined criteria.
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assign o_cyc_a = (~i_rst)&&((r_a_owner) ? i_a_cyc_a : i_b_cyc_a);
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assign o_cyc_a = ((r_a_owner) ? i_a_cyc_a : i_b_cyc_a);
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assign o_cyc_b = (~i_rst)&&((r_a_owner) ? i_a_cyc_b : i_b_cyc_b);
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assign o_cyc_b = ((r_a_owner) ? i_a_cyc_b : i_b_cyc_b);
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reg r_a_owner;
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reg r_a_owner;
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initial r_a_owner = 1'b1;
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initial r_a_owner = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_a_owner <= 1'b1;
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r_a_owner <= 1'b1;
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else if ((~o_cyc_a)&&(~o_cyc_b))
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else if ((~o_cyc_a)&&(~o_cyc_b))
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r_a_owner <= ((i_b_cyc_a)||(i_b_cyc_b))? 1'b0:1'b1;
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r_a_owner <= ((i_b_cyc_a)||(i_b_cyc_b))? 1'b0:1'b1;
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assign o_we = (r_a_owner) ? i_a_we : i_b_we;
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`ifdef ZERO_ON_IDLE
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//
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// ZERO_ON_IDLE uses more logic than the alternative. It should be
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// useful for reducing power, as these circuits tend to drive wires
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// all the way across the design, but it may also slow down the master
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// clock. I've used it as an option when using VERILATOR, 'cause
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// zeroing things on idle can make them stand out all the more when
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// staring at wires and dumps and such.
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//
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wire o_cyc, o_stb;
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assign o_cyc = ((o_cyc_a)||(o_cyc_b));
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assign o_stb = (o_cyc)&&((o_stb_a)||(o_stb_b));
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assign o_stb_a = (r_a_owner) ? (i_a_stb_a)&&(o_cyc_a) : (i_b_stb_a)&&(o_cyc_a);
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assign o_stb_b = (r_a_owner) ? (i_a_stb_b)&&(o_cyc_b) : (i_b_stb_b)&&(o_cyc_b);
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assign o_adr = ((o_stb_a)|(o_stb_b))?((r_a_owner) ? i_a_adr : i_b_adr):0;
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assign o_dat = (o_stb)?((r_a_owner) ? i_a_dat : i_b_dat):0;
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assign o_sel = (o_stb)?((r_a_owner) ? i_a_sel : i_b_sel):0;
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assign o_a_ack = (o_cyc)&&( r_a_owner) ? i_ack : 1'b0;
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assign o_b_ack = (o_cyc)&&(~r_a_owner) ? i_ack : 1'b0;
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assign o_a_stall = (o_cyc)&&( r_a_owner) ? i_stall : 1'b1;
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assign o_b_stall = (o_cyc)&&(~r_a_owner) ? i_stall : 1'b1;
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assign o_a_err = (o_cyc)&&( r_a_owner) ? i_err : 1'b0;
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assign o_b_err = (o_cyc)&&(~r_a_owner) ? i_err : 1'b0;
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`else
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// Realistically, if neither master owns the bus, the output is a
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// Realistically, if neither master owns the bus, the output is a
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// don't care. Thus we trigger off whether or not 'A' owns the bus.
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// don't care. Thus we trigger off whether or not 'A' owns the bus.
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// If 'B' owns it all we care is that 'A' does not. Likewise, if
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// If 'B' owns it all we care is that 'A' does not. Likewise, if
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// neither owns the bus than the values on these various lines are
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// neither owns the bus than the values on these various lines are
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// irrelevant.
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// irrelevant.
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assign o_stb_a = (r_a_owner) ? i_a_stb_a : i_b_stb_a;
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assign o_stb_a = (r_a_owner) ? i_a_stb_a : i_b_stb_a;
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assign o_stb_b = (r_a_owner) ? i_a_stb_b : i_b_stb_b;
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assign o_stb_b = (r_a_owner) ? i_a_stb_b : i_b_stb_b;
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assign o_we = (r_a_owner) ? i_a_we : i_b_we;
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assign o_we = (r_a_owner) ? i_a_we : i_b_we;
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assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr;
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assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr;
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assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat;
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assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat;
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assign o_sel = (r_a_owner) ? i_a_sel : i_b_sel;
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// We cannot allow the return acknowledgement to ever go high if
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// We cannot allow the return acknowledgement to ever go high if
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// the master in question does not own the bus. Hence we force it
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// the master in question does not own the bus. Hence we force it
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// low if the particular master doesn't own the bus.
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// low if the particular master doesn't own the bus.
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assign o_a_ack = ( r_a_owner) ? i_ack : 1'b0;
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assign o_a_ack = ( r_a_owner) ? i_ack : 1'b0;
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// These error lines will be implemented soon, as soon as the rest of
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// These error lines will be implemented soon, as soon as the rest of
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// the Zip CPU is ready to support them.
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// the Zip CPU is ready to support them.
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//
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//
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assign o_a_err = ( r_a_owner) ? i_err : 1'b0;
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assign o_a_err = ( r_a_owner) ? i_err : 1'b0;
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assign o_b_err = (~r_a_owner) ? i_err : 1'b0;
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assign o_b_err = (~r_a_owner) ? i_err : 1'b0;
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`endif
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endmodule
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endmodule
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