| Line 177... |
Line 177... |
cpu_dbg_cc, cpu_break,
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cpu_dbg_cc, cpu_break,
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o_wb_cyc, o_wb_stb,
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o_wb_cyc, o_wb_stb,
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cpu_lcl_cyc, cpu_lcl_stb,
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cpu_lcl_cyc, cpu_lcl_stb,
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o_wb_we, o_wb_addr, o_wb_data,
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o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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(i_wb_err)||((cpu_lcl_cyc)&&(cpu_lcl_stb)),
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(i_wb_err)||(cpu_lcl_cyc),
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cpu_op_stall, cpu_pf_stall, cpu_i_count
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cpu_op_stall, cpu_pf_stall, cpu_i_count
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`ifdef DEBUG_SCOPE
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`ifdef DEBUG_SCOPE
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, o_zip_debug
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, o_zip_debug
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`endif
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`endif
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);
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);
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| Line 206... |
Line 206... |
// Return debug response values
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// Return debug response values
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assign o_dbg_data = (~i_dbg_addr)?cmd_data :cpu_dbg_data;
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assign o_dbg_data = (~i_dbg_addr)?cmd_data :cpu_dbg_data;
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initial o_dbg_ack = 1'b0;
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initial o_dbg_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_dbg_ack <= (i_dbg_cyc)&&((~i_dbg_addr)||(~o_dbg_stall));
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o_dbg_ack <= (i_dbg_cyc)&&((~i_dbg_addr)||(~o_dbg_stall));
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assign o_dbg_stall=(i_dbg_cyc)&&(cpu_dbg_stall)&&(i_dbg_addr);
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assign o_dbg_stall= 1'b0; //(i_dbg_cyc)&&(cpu_dbg_stall)&&(i_dbg_addr);
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|
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assign o_ext_int = (cmd_halt) && (~i_wb_stall);
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assign o_ext_int = (cmd_halt) && (~i_wb_stall);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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