| Line 1864... |
Line 1864... |
`ifdef DEBUG_SCOPE
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`ifdef DEBUG_SCOPE
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// CLRPIP: If clear_pipeline, produce address ... can be 28 bits
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// CLRPIP: If clear_pipeline, produce address ... can be 28 bits
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// DATWR: If write value, produce 4-bits of register ID, 27 bits of value
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// DATWR: If write value, produce 4-bits of register ID, 27 bits of value
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// STALL: If neither, produce pipeline stall information
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// STALL: If neither, produce pipeline stall information
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// ADDR: If bus is valid, no ack, return the bus address
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// ADDR: If bus is valid, no ack, return the bus address
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wire this_write;
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assign this_write = ((mem_valid)||((~clear_pipeline)&&(~alu_illegal)
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&&(((alu_wr)&&(alu_valid))
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||(div_valid)||(fpu_valid))));
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reg last_write;
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always @(posedge i_clk)
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last_write <= this_write;
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reg [4:0] last_wreg;
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always @(posedge i_clk)
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last_wreg <= wr_reg_id;
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reg halt_primed;
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initial halt_primed = 0;
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always @(posedge i_clk)
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if (master_ce)
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halt_primed <= 1'b1;
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else if (debug_trigger)
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halt_primed <= 1'b0;
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reg [6:0] halt_count;
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initial halt_count = 0;
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always @(posedge i_clk)
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if ((i_rst)||(!i_halt)||(r_halted)||(!halt_primed))
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halt_count <= 0;
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else if (!(&halt_count))
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halt_count <= halt_count + 1'b1;
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reg [9:0] mem_counter;
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initial mem_counter = 0;
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always @(posedge i_clk)
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if ((i_rst)||(!halt_primed)||(!mem_busy))
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mem_counter <= 0;
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else if (!(&mem_counter))
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mem_counter <= mem_counter + 1'b1;
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reg [15:0] long_trigger;
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always @(posedge i_clk)
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long_trigger[15:1] <= long_trigger[14:0];
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always @(posedge i_clk)
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long_trigger[0] <= ((last_write)&&(last_wreg == wr_reg_id))
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||(&halt_count)||(&mem_counter);
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reg debug_trigger;
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reg debug_trigger;
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initial debug_trigger = 1'b0;
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initial debug_trigger = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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debug_trigger <= (!i_halt)&&(o_break);
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debug_trigger <= (!i_halt)&&(o_break)||(long_trigger == 16'hffff);
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wire [31:0] debug_flags;
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wire [31:0] debug_flags;
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assign debug_flags = { debug_trigger, 3'b101,
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assign debug_flags = { debug_trigger, 3'b101,
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master_ce, i_halt, o_break, sleep,
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master_ce, i_halt, o_break, sleep,
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gie, ibus_err_flag, trap, ill_err_i,
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gie, ibus_err_flag, trap, ill_err_i,
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| Line 1879... |
Line 1922... |
dcdvalid, dcd_stalled, op_ce, opvalid,
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dcdvalid, dcd_stalled, op_ce, opvalid,
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op_pipe, alu_ce, alu_busy, alu_wr,
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op_pipe, alu_ce, alu_busy, alu_wr,
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alu_illegal, alF_wr, mem_ce, mem_we,
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alu_illegal, alF_wr, mem_ce, mem_we,
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mem_busy, mem_pipe_stalled, (new_pc), (dcd_early_branch) };
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mem_busy, mem_pipe_stalled, (new_pc), (dcd_early_branch) };
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wire [25:0] bus_debug;
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assign bus_debug = { debug_trigger,
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mem_ce, mem_we, mem_busy, mem_pipe_stalled,
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o_wb_gbl_cyc, o_wb_gbl_stb, o_wb_lcl_cyc, o_wb_lcl_stb,
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o_wb_we, i_wb_ack, i_wb_stall, i_wb_err,
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pf_cyc, pf_stb, pf_ack, pf_stall,
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pf_err,
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mem_cyc_gbl, mem_stb_gbl, mem_cyc_lcl, mem_stb_lcl,
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mem_we, mem_ack, mem_stall, mem_err
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};
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if ((i_halt)||(!master_ce)||(debug_trigger)||(o_break))
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if ((i_halt)||(!master_ce)||(debug_trigger)||(o_break))
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o_debug <= debug_flags;
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o_debug <= debug_flags;
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else if ((mem_valid)||((~clear_pipeline)&&(~alu_illegal)
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else if ((mem_valid)||((~clear_pipeline)&&(~alu_illegal)
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| Line 1894... |
Line 1948... |
else if ((o_wb_gbl_stb)|(o_wb_lcl_stb))
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else if ((o_wb_gbl_stb)|(o_wb_lcl_stb))
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o_debug <= {debug_trigger, 2'b11, o_wb_gbl_stb, o_wb_we,
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o_debug <= {debug_trigger, 2'b11, o_wb_gbl_stb, o_wb_we,
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(o_wb_we)?o_wb_data[26:0] : o_wb_addr[26:0] };
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(o_wb_we)?o_wb_data[26:0] : o_wb_addr[26:0] };
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else
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else
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o_debug <= debug_flags;
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o_debug <= debug_flags;
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// o_debug[25:0] <= bus_debug;
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end
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end
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`endif
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`endif
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endmodule
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endmodule
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