| Line 201... |
Line 201... |
// optimizes logic away, to where it no longer works. The logic
|
// optimizes logic away, to where it no longer works. The logic
|
// as described herein will work, this just makes sure XST implements
|
// as described herein will work, this just makes sure XST implements
|
// that logic.
|
// that logic.
|
//
|
//
|
(* ram_style = "distributed" *)
|
(* ram_style = "distributed" *)
|
|
`ifdef OPT_NO_USERMODE
|
|
reg [31:0] regset [0:15];
|
|
`else
|
reg [31:0] regset [0:31];
|
reg [31:0] regset [0:31];
|
|
`endif
|
|
|
// Condition codes
|
// Condition codes
|
// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
|
// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
|
reg [3:0] flags, iflags;
|
reg [3:0] flags, iflags;
|
wire [14:0] w_uflags, w_iflags;
|
wire [14:0] w_uflags, w_iflags;
|
reg trap, break_en, step, gie, sleep, r_halted;
|
reg break_en, step, sleep, r_halted;
|
wire break_pending;
|
wire break_pending, trap, gie, ubreak;
|
wire w_clear_icache;
|
wire w_clear_icache, ill_err_u;
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
reg ill_err_u, ill_err_i;
|
reg ill_err_i;
|
`else
|
`else
|
wire ill_err_u, ill_err_i;
|
wire ill_err_i;
|
`endif
|
`endif
|
reg ubreak;
|
reg ibus_err_flag;
|
reg ibus_err_flag, ubus_err_flag;
|
wire ubus_err_flag;
|
wire idiv_err_flag, udiv_err_flag;
|
wire idiv_err_flag, udiv_err_flag;
|
wire ifpu_err_flag, ufpu_err_flag;
|
wire ifpu_err_flag, ufpu_err_flag;
|
wire ihalt_phase, uhalt_phase;
|
wire ihalt_phase, uhalt_phase;
|
|
|
// The master chip enable
|
// The master chip enable
|
| Line 328... |
Line 332... |
wire alu_gie, alu_illegal;
|
wire alu_gie, alu_illegal;
|
|
|
|
|
|
|
wire mem_ce, mem_stalled;
|
wire mem_ce, mem_stalled;
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
|
wire mem_pipe_stalled;
|
wire mem_pipe_stalled;
|
`endif
|
|
wire mem_valid, mem_ack, mem_stall, mem_err, bus_err,
|
wire mem_valid, mem_ack, mem_stall, mem_err, bus_err,
|
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
|
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
|
wire [4:0] mem_wreg;
|
wire [4:0] mem_wreg;
|
|
|
wire mem_busy, mem_rdbusy;
|
wire mem_busy, mem_rdbusy;
|
| Line 367... |
Line 369... |
wire wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc,
|
wire wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc,
|
wr_write_scc, wr_write_ucc;
|
wr_write_scc, wr_write_ucc;
|
wire [4:0] wr_reg_id;
|
wire [4:0] wr_reg_id;
|
wire [31:0] wr_gpreg_vl, wr_spreg_vl;
|
wire [31:0] wr_gpreg_vl, wr_spreg_vl;
|
wire w_switch_to_interrupt, w_release_from_interrupt;
|
wire w_switch_to_interrupt, w_release_from_interrupt;
|
reg [(AW-1):0] upc, ipc;
|
reg [(AW-1):0] ipc;
|
|
wire [(AW-1):0] upc;
|
|
|
|
|
|
|
//
|
//
|
// MASTER: clock enable.
|
// MASTER: clock enable.
|
| Line 443... |
Line 446... |
||(dcdB_stall)
|
||(dcdB_stall)
|
// Or if we need to wait on flags to work on the
|
// Or if we need to wait on flags to work on the
|
// CC register
|
// CC register
|
||(dcdF_stall)
|
||(dcdF_stall)
|
);
|
);
|
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
|
assign op_ce = ((dcdvalid)||(dcd_illegal)||(dcd_early_branch))&&(~op_stall)&&(~clear_pipeline);
|
|
|
|
|
// BUT ... op_ce is too complex for many of the data operations. So
|
// BUT ... op_ce is too complex for many of the data operations. So
|
// let's make their circuit enable code simpler. In particular, if
|
// let's make their circuit enable code simpler. In particular, if
|
// op_ doesn't need to be preserved, we can change it all we want
|
// op_ doesn't need to be preserved, we can change it all we want
|
// ... right? The clear_pipeline code, for example, really only needs
|
// ... right? The clear_pipeline code, for example, really only needs
|
// to determine whether opvalid is true.
|
// to determine whether opvalid is true.
|
assign op_change_data_ce = (~op_stall);
|
assign op_change_data_ce = (~op_stall);
|
`else
|
`else
|
assign op_stall = (opvalid)&&(~master_ce);
|
assign op_stall = (opvalid)&&(~master_ce);
|
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline);
|
assign op_ce = ((dcdvalid)||(dcd_illegal)||(dcd_early_branch))&&(~clear_pipeline);
|
assign op_change_data_ce = 1'b1;
|
assign op_change_data_ce = 1'b1;
|
`endif
|
`endif
|
|
|
//
|
//
|
// PIPELINE STAGE #4 :: ALU / Memory
|
// PIPELINE STAGE #4 :: ALU / Memory
|
| Line 474... |
Line 477... |
// through the ALU. Break instructions are not allowed through
|
// through the ALU. Break instructions are not allowed through
|
// the ALU.
|
// the ALU.
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2
|
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2
|
||((opvalid)&&(op_lock)&&(op_lock_stall))
|
||((opvalid)&&(op_lock)&&(op_lock_stall))
|
||((opvalid)&&(op_break)) // || op_illegal
|
||((opvalid)&&(op_break))
|
||(wr_reg_ce)&&(wr_write_cc)
|
||(wr_reg_ce)&&(wr_write_cc)
|
||(div_busy)||(fpu_busy);
|
||(div_busy)||(fpu_busy);
|
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)
|
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)
|
&&(~clear_pipeline);
|
&&(~clear_pipeline);
|
`else
|
`else
|
| Line 592... |
Line 595... |
//||
|
//||
|
//`endif
|
//`endif
|
(mem_cyc_lcl)||(mem_cyc_gbl),
|
(mem_cyc_lcl)||(mem_cyc_gbl),
|
pf_illegal);
|
pf_illegal);
|
`endif
|
`endif
|
|
`ifdef OPT_NO_USERMODE
|
|
assign instruction_gie = 1'b0;
|
|
`else
|
assign instruction_gie = gie;
|
assign instruction_gie = gie;
|
|
`endif
|
|
|
initial r_dcdvalid = 1'b0;
|
initial r_dcdvalid = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(clear_pipeline)||(w_clear_icache))
|
if ((i_rst)||(clear_pipeline)||(w_clear_icache))
|
r_dcdvalid <= 1'b0;
|
r_dcdvalid <= 1'b0;
|
| Line 671... |
Line 678... |
//
|
//
|
//
|
//
|
// PIPELINE STAGE #3 :: Read Operands (Registers)
|
// PIPELINE STAGE #3 :: Read Operands (Registers)
|
//
|
//
|
//
|
//
|
|
`ifdef OPT_NO_USERMODE
|
|
assign w_opA = regset[dcdA[3:0]];
|
|
assign w_opB = regset[dcdB[3:0]];
|
|
`else
|
assign w_opA = regset[dcdA];
|
assign w_opA = regset[dcdA];
|
assign w_opB = regset[dcdB];
|
assign w_opB = regset[dcdB];
|
|
`endif
|
|
|
wire [8:0] w_cpu_info;
|
wire [8:0] w_cpu_info;
|
assign w_cpu_info = {
|
assign w_cpu_info = {
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
1'b1,
|
1'b1,
|
| Line 841... |
Line 853... |
endcase
|
endcase
|
end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
|
end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
|
assign opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
|
assign opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
|
|
|
wire w_opvalid;
|
wire w_opvalid;
|
assign w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp);
|
assign w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp)&&(!dcd_early_branch);
|
initial opvalid = 1'b0;
|
initial opvalid = 1'b0;
|
initial opvalid_alu = 1'b0;
|
initial opvalid_alu = 1'b0;
|
initial opvalid_mem = 1'b0;
|
initial opvalid_mem = 1'b0;
|
initial opvalid_div = 1'b0;
|
initial opvalid_div = 1'b0;
|
initial opvalid_fpu = 1'b0;
|
initial opvalid_fpu = 1'b0;
|
| Line 865... |
Line 877... |
// have in our queue. This instruction must then
|
// have in our queue. This instruction must then
|
// move forward, and get a stall cycle inserted.
|
// move forward, and get a stall cycle inserted.
|
// Hence, the test on dcd_stalled here. If we must
|
// Hence, the test on dcd_stalled here. If we must
|
// wait until our operands are valid, then we aren't
|
// wait until our operands are valid, then we aren't
|
// valid yet until then.
|
// valid yet until then.
|
opvalid<= (w_opvalid)||(dcd_illegal)&&(dcdvalid);
|
opvalid<= (w_opvalid)||(dcd_illegal)&&(dcdvalid)||(dcd_early_branch);
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
opvalid_alu <= (w_opvalid)&&((dcdALU)||(dcd_illegal));
|
opvalid_alu <= (w_opvalid)&&((dcdALU)||(dcd_illegal)
|
|
||(dcd_early_branch));
|
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid);
|
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid);
|
opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid);
|
opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid);
|
opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid);
|
opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid);
|
`else
|
`else
|
opvalid_alu <= (dcdALU)&&(w_opvalid);
|
opvalid_alu <= (dcdALU)&&(w_opvalid)||(dcd_early_branch);
|
opvalid_mem <= (dcdM)&&(w_opvalid);
|
opvalid_mem <= (dcdM)&&(w_opvalid);
|
opvalid_div <= (dcdDV)&&(w_opvalid);
|
opvalid_div <= (dcdDV)&&(w_opvalid);
|
opvalid_fpu <= (dcdFP)&&(w_opvalid);
|
opvalid_fpu <= (dcdFP)&&(w_opvalid);
|
`endif
|
`endif
|
end else if ((adf_ce_unconditional)||(mem_ce))
|
end else if ((adf_ce_unconditional)||(mem_ce))
|
| Line 901... |
Line 914... |
reg r_op_break;
|
reg r_op_break;
|
|
|
initial r_op_break = 1'b0;
|
initial r_op_break = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst) r_op_break <= 1'b0;
|
if (i_rst) r_op_break <= 1'b0;
|
else if (op_ce) r_op_break <= (dcd_break); //||dcd_illegal &&(dcdvalid)
|
else if (op_ce) r_op_break <= (dcd_break);
|
else if ((clear_pipeline)||(~opvalid))
|
else if ((clear_pipeline)||(~opvalid))
|
r_op_break <= 1'b0;
|
r_op_break <= 1'b0;
|
assign op_break = r_op_break;
|
assign op_break = r_op_break;
|
`else
|
`else
|
assign op_break = dcd_break;
|
assign op_break = dcd_break;
|
| Line 986... |
Line 999... |
reg r_opR_cc;
|
reg r_opR_cc;
|
reg r_op_gie;
|
reg r_op_gie;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_change_data_ce)
|
if (op_change_data_ce)
|
begin
|
begin
|
r_opn <= dcdOp; // Which ALU operation?
|
// Which ALU operation? Early branches are
|
|
// unimplemented moves
|
|
r_opn <= (dcd_early_branch) ? 4'hf : dcdOp;
|
// opM <= dcdM; // Is this a memory operation?
|
// opM <= dcdM; // Is this a memory operation?
|
// What register will these results be written into?
|
// What register will these results be written into?
|
r_opR <= dcdR;
|
r_opR <= dcdR;
|
r_opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie);
|
r_opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie);
|
// User level (1), vs supervisor (0)/interrupts disabled
|
// User level (1), vs supervisor (0)/interrupts disabled
|
r_op_gie <= dcd_gie;
|
r_op_gie <= dcd_gie;
|
|
|
|
|
//
|
//
|
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
|
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
|
end
|
end
|
assign opn = r_opn;
|
assign opn = r_opn;
|
assign opR = r_opR;
|
assign opR = r_opR;
|
|
`ifdef OPT_NO_USERMODE
|
|
assign op_gie = 1'b0;
|
|
`else
|
assign op_gie = r_op_gie;
|
assign op_gie = r_op_gie;
|
|
`endif
|
assign opR_cc = r_opR_cc;
|
assign opR_cc = r_opR_cc;
|
`else
|
`else
|
assign opn = dcdOp;
|
assign opn = dcdOp;
|
assign opR = dcdR;
|
assign opR = dcdR;
|
|
`ifdef OPT_NO_USERMODE
|
|
assign op_gie = 1'b0;
|
|
`else
|
assign op_gie = dcd_gie;
|
assign op_gie = dcd_gie;
|
|
`endif
|
// With no pipelining, there is no early branching. We keep it
|
// With no pipelining, there is no early branching. We keep it
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
|
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
|
`endif
|
`endif
|
assign opFl = (op_gie)?(w_uflags):(w_iflags);
|
assign opFl = (op_gie)?(w_uflags):(w_iflags);
|
| Line 1227... |
Line 1249... |
always @(posedge i_clk)
|
always @(posedge i_clk)
|
dbgv <= (~i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
|
dbgv <= (~i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
|
reg [31:0] dbg_val;
|
reg [31:0] dbg_val;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
dbg_val <= i_dbg_data;
|
dbg_val <= i_dbg_data;
|
|
`ifdef OPT_NO_USERMODE
|
|
assign alu_gie = 1'b0;
|
|
`else
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
reg r_alu_gie;
|
reg r_alu_gie;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((adf_ce_unconditional)||(mem_ce))
|
if ((adf_ce_unconditional)||(mem_ce))
|
r_alu_gie <= op_gie;
|
r_alu_gie <= op_gie;
|
assign alu_gie = r_alu_gie;
|
assign alu_gie = r_alu_gie;
|
|
`else
|
|
assign alu_gie = op_gie;
|
|
`endif
|
|
`endif
|
|
|
|
`ifdef OPT_PIPELINED
|
reg [(AW-1):0] r_alu_pc;
|
reg [(AW-1):0] r_alu_pc;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((adf_ce_unconditional)
|
if ((adf_ce_unconditional)
|
||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
|
||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
|
&&(~mem_stalled)))
|
&&(~mem_stalled)))
|
r_alu_pc <= op_pc;
|
r_alu_pc <= op_pc;
|
assign alu_pc = r_alu_pc;
|
assign alu_pc = r_alu_pc;
|
`else
|
`else
|
assign alu_gie = op_gie;
|
|
assign alu_pc = op_pc;
|
assign alu_pc = op_pc;
|
`endif
|
`endif
|
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
reg r_alu_illegal;
|
reg r_alu_illegal;
|
| Line 1319... |
Line 1348... |
mem_valid, bus_err, mem_wreg, mem_result,
|
mem_valid, bus_err, mem_wreg, mem_result,
|
mem_cyc_gbl, mem_cyc_lcl,
|
mem_cyc_gbl, mem_cyc_lcl,
|
mem_stb_gbl, mem_stb_lcl,
|
mem_stb_gbl, mem_stb_lcl,
|
mem_we, mem_addr, mem_data,
|
mem_we, mem_addr, mem_data,
|
mem_ack, mem_stall, mem_err, i_wb_data);
|
mem_ack, mem_stall, mem_err, i_wb_data);
|
|
assign mem_pipe_stalled = 1'b0;
|
`endif // PIPELINED_BUS_ACCESS
|
`endif // PIPELINED_BUS_ACCESS
|
assign mem_rdbusy = ((mem_busy)&&(~mem_we));
|
assign mem_rdbusy = ((mem_busy)&&(~mem_we));
|
|
|
// Either the prefetch or the instruction gets the memory bus, but
|
// Either the prefetch or the instruction gets the memory bus, but
|
// never both.
|
// never both.
|
| Line 1378... |
Line 1408... |
// Which register shall be written?
|
// Which register shall be written?
|
// COULD SIMPLIFY THIS: by adding three bits to these registers,
|
// COULD SIMPLIFY THIS: by adding three bits to these registers,
|
// One or PC, one for CC, and one for GIE match
|
// One or PC, one for CC, and one for GIE match
|
// Note that the alu_reg is the register to write on a divide or
|
// Note that the alu_reg is the register to write on a divide or
|
// FPU operation.
|
// FPU operation.
|
|
`ifdef OPT_NO_USERMODE
|
|
assign wr_reg_id[3:0] = (alu_wr|div_valid|fpu_valid)
|
|
? alu_reg[3:0]:mem_wreg[3:0];
|
|
assign wr_reg_id[4] = 1'b0;
|
|
`else
|
assign wr_reg_id = (alu_wr|div_valid|fpu_valid)?alu_reg:mem_wreg;
|
assign wr_reg_id = (alu_wr|div_valid|fpu_valid)?alu_reg:mem_wreg;
|
|
`endif
|
|
|
// Are we writing to the CC register?
|
// Are we writing to the CC register?
|
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
|
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
|
assign wr_write_scc = (wr_reg_id[4:0] == {1'b0, `CPU_CC_REG});
|
assign wr_write_scc = (wr_reg_id[4:0] == {1'b0, `CPU_CC_REG});
|
assign wr_write_ucc = (wr_reg_id[4:0] == {1'b1, `CPU_CC_REG});
|
assign wr_write_ucc = (wr_reg_id[4:0] == {1'b1, `CPU_CC_REG});
|
// Are we writing to the PC?
|
// Are we writing to the PC?
|
| Line 1395... |
Line 1432... |
:((dbgv) ? dbg_val : alu_result));
|
:((dbgv) ? dbg_val : alu_result));
|
assign wr_spreg_vl = ((mem_valid) ? mem_result
|
assign wr_spreg_vl = ((mem_valid) ? mem_result
|
:((dbgv) ? dbg_val : alu_result));
|
:((dbgv) ? dbg_val : alu_result));
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (wr_reg_ce)
|
if (wr_reg_ce)
|
|
`ifdef OPT_NO_USERMODE
|
|
regset[wr_reg_id[3:0]] <= wr_gpreg_vl;
|
|
`else
|
regset[wr_reg_id] <= wr_gpreg_vl;
|
regset[wr_reg_id] <= wr_gpreg_vl;
|
|
`endif
|
|
|
//
|
//
|
// Write back to the condition codes/flags register ...
|
// Write back to the condition codes/flags register ...
|
// When shall we write to our flags register? alF_wr already
|
// When shall we write to our flags register? alF_wr already
|
// includes the set condition ...
|
// includes the set condition ...
|
| Line 1481... |
Line 1522... |
// sleep until the next interrupt. Setting the sleep register within
|
// sleep until the next interrupt. Setting the sleep register within
|
// interrupt mode causes the processor to halt until a reset. This is
|
// interrupt mode causes the processor to halt until a reset. This is
|
// a panic/fault halt. The trick is that you cannot be allowed to
|
// a panic/fault halt. The trick is that you cannot be allowed to
|
// set the sleep bit and switch to supervisor mode in the same
|
// set the sleep bit and switch to supervisor mode in the same
|
// instruction: users are not allowed to halt the CPU.
|
// instruction: users are not allowed to halt the CPU.
|
|
initial sleep = 1'b0;
|
|
`ifdef OPT_NO_USERMODE
|
|
reg r_sleep_is_halt;
|
|
initial r_sleep_is_halt = 1'b0;
|
|
always @(posedge i_clk)
|
|
if (i_rst)
|
|
r_sleep_is_halt <= 1'b0;
|
|
else if ((wr_reg_ce)&&(wr_write_cc)
|
|
&&(wr_spreg_vl[`CPU_SLEEP_BIT])
|
|
&&(~wr_spreg_vl[`CPU_GIE_BIT]))
|
|
r_sleep_is_halt <= 1'b1;
|
|
|
|
// Trying to switch to user mode, either via a WAIT or an RTU
|
|
// instruction will cause the CPU to sleep until an interrupt, in
|
|
// the NO-USERMODE build.
|
|
always @(posedge i_clk)
|
|
if ((i_rst)||((i_interrupt)&&(!r_sleep_is_halt)))
|
|
sleep <= 1'b0;
|
|
else if ((wr_reg_ce)&&(wr_write_cc)
|
|
&&(wr_spreg_vl[`CPU_GIE_BIT]))
|
|
sleep <= 1'b1;
|
|
`else
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(w_switch_to_interrupt))
|
if ((i_rst)||(w_switch_to_interrupt))
|
sleep <= 1'b0;
|
sleep <= 1'b0;
|
else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
|
else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
|
// In supervisor mode, we have no protections. The
|
// In supervisor mode, we have no protections. The
|
| Line 1501... |
Line 1564... |
// In user mode, however, you can only set the sleep
|
// In user mode, however, you can only set the sleep
|
// mode while remaining in user mode. You can't switch
|
// mode while remaining in user mode. You can't switch
|
// to sleep mode *and* supervisor mode at the same
|
// to sleep mode *and* supervisor mode at the same
|
// time, lest you halt the CPU.
|
// time, lest you halt the CPU.
|
sleep <= wr_spreg_vl[`CPU_SLEEP_BIT];
|
sleep <= wr_spreg_vl[`CPU_SLEEP_BIT];
|
|
`endif
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
step <= 1'b0;
|
step <= 1'b0;
|
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_write_ucc))
|
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_write_ucc))
|
step <= wr_spreg_vl[`CPU_STEP_BIT];
|
step <= wr_spreg_vl[`CPU_STEP_BIT];
|
|
|
// The GIE register. Only interrupts can disable the interrupt register
|
// The GIE register. Only interrupts can disable the interrupt register
|
|
`ifdef OPT_NO_USERMODE
|
|
assign w_switch_to_interrupt = 1'b0;
|
|
assign w_release_from_interrupt = 1'b0;
|
|
`else
|
assign w_switch_to_interrupt = (gie)&&(
|
assign w_switch_to_interrupt = (gie)&&(
|
// On interrupt (obviously)
|
// On interrupt (obviously)
|
((i_interrupt)&&(~alu_phase)&&(~bus_lock))
|
((i_interrupt)&&(~alu_phase)&&(~bus_lock))
|
// If we are stepping the CPU
|
// If we are stepping the CPU
|
||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(~alu_phase)&&(~bus_lock))
|
||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(~alu_phase)&&(~bus_lock))
|
| Line 1540... |
Line 1608... |
assign w_release_from_interrupt = (~gie)&&(~i_interrupt)
|
assign w_release_from_interrupt = (~gie)&&(~i_interrupt)
|
// Then if we write the sCC register
|
// Then if we write the sCC register
|
&&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT])
|
&&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT])
|
&&(wr_write_scc))
|
&&(wr_write_scc))
|
);
|
);
|
|
`endif
|
|
|
|
`ifdef OPT_NO_USERMODE
|
|
assign gie = 1'b0;
|
|
`else
|
|
reg r_gie;
|
|
|
|
initial r_gie = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
gie <= 1'b0;
|
r_gie <= 1'b0;
|
else if (w_switch_to_interrupt)
|
else if (w_switch_to_interrupt)
|
gie <= 1'b0;
|
r_gie <= 1'b0;
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
gie <= 1'b1;
|
r_gie <= 1'b1;
|
|
assign gie = r_gie;
|
|
`endif
|
|
|
|
`ifdef OPT_NO_USERMODE
|
|
assign trap = 1'b0;
|
|
assign ubreak = 1'b0;
|
|
`else
|
|
reg r_trap;
|
|
|
initial trap = 1'b0;
|
initial r_trap = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(w_release_from_interrupt))
|
if ((i_rst)||(w_release_from_interrupt))
|
trap <= 1'b0;
|
r_trap <= 1'b0;
|
else if ((alu_gie)&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
|
else if ((alu_gie)&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
|
&&(wr_write_ucc)) // &&(wr_reg_id[4]) implied
|
&&(wr_write_ucc)) // &&(wr_reg_id[4]) implied
|
trap <= 1'b1;
|
r_trap <= 1'b1;
|
else if ((wr_reg_ce)&&(wr_write_ucc)&&(~alu_gie))
|
else if ((wr_reg_ce)&&(wr_write_ucc)&&(~alu_gie))
|
trap <= (trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]);
|
r_trap <= (r_trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]);
|
|
|
|
reg r_ubreak;
|
|
|
initial ubreak = 1'b0;
|
initial r_ubreak = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(w_release_from_interrupt))
|
if ((i_rst)||(w_release_from_interrupt))
|
ubreak <= 1'b0;
|
r_ubreak <= 1'b0;
|
else if ((op_gie)&&(break_pending)&&(w_switch_to_interrupt))
|
else if ((op_gie)&&(break_pending)&&(w_switch_to_interrupt))
|
ubreak <= 1'b1;
|
r_ubreak <= 1'b1;
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
|
ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]);
|
r_ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]);
|
|
|
|
assign trap = r_trap;
|
|
assign ubreak = r_ubreak;
|
|
`endif
|
|
|
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
initial ill_err_i = 1'b0;
|
initial ill_err_i = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
| Line 1578... |
Line 1668... |
// Only the debug interface can clear this bit
|
// Only the debug interface can clear this bit
|
else if ((dbgv)&&(wr_write_scc))
|
else if ((dbgv)&&(wr_write_scc))
|
ill_err_i <= (ill_err_i)&&(wr_spreg_vl[`CPU_ILL_BIT]);
|
ill_err_i <= (ill_err_i)&&(wr_spreg_vl[`CPU_ILL_BIT]);
|
else if ((alu_illegal)&&(~alu_gie)&&(!clear_pipeline))
|
else if ((alu_illegal)&&(~alu_gie)&&(!clear_pipeline))
|
ill_err_i <= 1'b1;
|
ill_err_i <= 1'b1;
|
initial ill_err_u = 1'b0;
|
|
|
`ifdef OPT_NO_USERMODE
|
|
assign ill_err_u = 1'b0;
|
|
`else
|
|
reg r_ill_err_u;
|
|
|
|
initial r_ill_err_u = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
// The bit is automatically cleared on release from interrupt
|
// The bit is automatically cleared on release from interrupt
|
// or reset
|
// or reset
|
if ((i_rst)||(w_release_from_interrupt))
|
if ((i_rst)||(w_release_from_interrupt))
|
ill_err_u <= 1'b0;
|
r_ill_err_u <= 1'b0;
|
// If the supervisor (or debugger) writes to this register,
|
// If the supervisor (or debugger) writes to this register,
|
// clearing the bit, then clear it
|
// clearing the bit, then clear it
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
|
ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT]));
|
r_ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT]));
|
else if ((alu_illegal)&&(alu_gie)&&(!clear_pipeline))
|
else if ((alu_illegal)&&(alu_gie)&&(!clear_pipeline))
|
ill_err_u <= 1'b1;
|
r_ill_err_u <= 1'b1;
|
|
`endif
|
`else
|
`else
|
assign ill_err_u = 1'b0;
|
assign ill_err_u = 1'b0;
|
assign ill_err_i = 1'b0;
|
assign ill_err_i = 1'b0;
|
`endif
|
`endif
|
// Supervisor/interrupt bus error flag -- this will crash the CPU if
|
// Supervisor/interrupt bus error flag -- this will crash the CPU if
|
| Line 1606... |
Line 1703... |
ibus_err_flag <= (ibus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
|
ibus_err_flag <= (ibus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
|
else if ((bus_err)&&(~alu_gie))
|
else if ((bus_err)&&(~alu_gie))
|
ibus_err_flag <= 1'b1;
|
ibus_err_flag <= 1'b1;
|
// User bus error flag -- if ever set, it will cause an interrupt to
|
// User bus error flag -- if ever set, it will cause an interrupt to
|
// supervisor mode.
|
// supervisor mode.
|
initial ubus_err_flag = 1'b0;
|
`ifdef OPT_NO_USERMODE
|
|
assign ubus_err_flag = 1'b0;
|
|
`else
|
|
reg r_ubus_err_flag;
|
|
|
|
initial r_ubus_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(w_release_from_interrupt))
|
if ((i_rst)||(w_release_from_interrupt))
|
ubus_err_flag <= 1'b0;
|
r_ubus_err_flag <= 1'b0;
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
|
ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
|
r_ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
|
else if ((bus_err)&&(alu_gie))
|
else if ((bus_err)&&(alu_gie))
|
ubus_err_flag <= 1'b1;
|
r_ubus_err_flag <= 1'b1;
|
|
|
|
assign ubus_err_flag = r_ubus_err_flag;
|
|
`endif
|
|
|
generate
|
generate
|
if (IMPLEMENT_DIVIDE != 0)
|
if (IMPLEMENT_DIVIDE != 0)
|
begin
|
begin
|
reg r_idiv_err_flag, r_udiv_err_flag;
|
reg r_idiv_err_flag, r_udiv_err_flag;
|
| Line 1631... |
Line 1736... |
r_idiv_err_flag <= 1'b0;
|
r_idiv_err_flag <= 1'b0;
|
else if ((dbgv)&&(wr_write_scc))
|
else if ((dbgv)&&(wr_write_scc))
|
r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
|
r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
|
else if ((div_error)&&(~alu_gie))
|
else if ((div_error)&&(~alu_gie))
|
r_idiv_err_flag <= 1'b1;
|
r_idiv_err_flag <= 1'b1;
|
|
|
|
assign idiv_err_flag = r_idiv_err_flag;
|
|
`ifdef OPT_NO_USERMODE
|
|
assign udiv_err_flag = 1'b0;
|
|
`else
|
// User divide (by zero) error flag -- if ever set, it will
|
// User divide (by zero) error flag -- if ever set, it will
|
// cause a sudden switch interrupt to supervisor mode.
|
// cause a sudden switch interrupt to supervisor mode.
|
initial r_udiv_err_flag = 1'b0;
|
initial r_udiv_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(w_release_from_interrupt))
|
if ((i_rst)||(w_release_from_interrupt))
|
| Line 1643... |
Line 1753... |
&&(wr_write_ucc))
|
&&(wr_write_ucc))
|
r_udiv_err_flag <= (r_udiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
|
r_udiv_err_flag <= (r_udiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
|
else if ((div_error)&&(alu_gie))
|
else if ((div_error)&&(alu_gie))
|
r_udiv_err_flag <= 1'b1;
|
r_udiv_err_flag <= 1'b1;
|
|
|
assign idiv_err_flag = r_idiv_err_flag;
|
|
assign udiv_err_flag = r_udiv_err_flag;
|
assign udiv_err_flag = r_udiv_err_flag;
|
|
`endif
|
end else begin
|
end else begin
|
assign idiv_err_flag = 1'b0;
|
assign idiv_err_flag = 1'b0;
|
assign udiv_err_flag = 1'b0;
|
assign udiv_err_flag = 1'b0;
|
end endgenerate
|
end endgenerate
|
|
|
| Line 1684... |
Line 1794... |
assign ifpu_err_flag = 1'b0;
|
assign ifpu_err_flag = 1'b0;
|
assign ufpu_err_flag = 1'b0;
|
assign ufpu_err_flag = 1'b0;
|
end endgenerate
|
end endgenerate
|
|
|
`ifdef OPT_VLIW
|
`ifdef OPT_VLIW
|
reg r_ihalt_phase, r_uhalt_phase;
|
reg r_ihalt_phase;
|
|
|
initial r_ihalt_phase = 0;
|
initial r_ihalt_phase = 0;
|
initial r_uhalt_phase = 0;
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_ihalt_phase <= 1'b0;
|
r_ihalt_phase <= 1'b0;
|
else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
|
else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
|
r_ihalt_phase <= alu_phase;
|
r_ihalt_phase <= alu_phase;
|
|
|
|
assign ihalt_phase = r_ihalt_phase;
|
|
|
|
`ifdef OPT_NO_USERMODE
|
|
assign uhalt_phase = 1'b0;
|
|
`else
|
|
reg r_uhalt_phase;
|
|
|
|
initial r_uhalt_phase = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(w_release_from_interrupt))
|
if ((i_rst)||(w_release_from_interrupt))
|
r_uhalt_phase <= 1'b0;
|
r_uhalt_phase <= 1'b0;
|
else if ((alu_gie)&&(alu_pc_valid))
|
else if ((alu_gie)&&(alu_pc_valid))
|
r_uhalt_phase <= alu_phase;
|
r_uhalt_phase <= alu_phase;
|
else if ((~alu_gie)&&(wr_reg_ce)&&(wr_write_ucc))
|
else if ((~alu_gie)&&(wr_reg_ce)&&(wr_write_ucc))
|
r_uhalt_phase <= wr_spreg_vl[`CPU_PHASE_BIT];
|
r_uhalt_phase <= wr_spreg_vl[`CPU_PHASE_BIT];
|
|
|
assign ihalt_phase = r_ihalt_phase;
|
|
assign uhalt_phase = r_uhalt_phase;
|
assign uhalt_phase = r_uhalt_phase;
|
|
`endif
|
`else
|
`else
|
assign ihalt_phase = 1'b0;
|
assign ihalt_phase = 1'b0;
|
assign uhalt_phase = 1'b0;
|
assign uhalt_phase = 1'b0;
|
`endif
|
`endif
|
|
|
| Line 1718... |
Line 1836... |
//
|
//
|
// Do we need to all our partial results from the pipeline?
|
// Do we need to all our partial results from the pipeline?
|
// What happens when the pipeline has gie and ~gie instructions within
|
// What happens when the pipeline has gie and ~gie instructions within
|
// it? Do we clear both? What if a gie instruction tries to clear
|
// it? Do we clear both? What if a gie instruction tries to clear
|
// a non-gie instruction?
|
// a non-gie instruction?
|
|
`ifdef OPT_NO_USERMODE
|
|
assign upc = {(AW){1'b0}};
|
|
`else
|
|
reg [(AW-1):0] r_upc;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
|
upc <= wr_spreg_vl[(AW-1):0];
|
r_upc <= wr_spreg_vl[(AW-1):0];
|
else if ((alu_gie)&&
|
else if ((alu_gie)&&
|
(((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal))
|
(((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal))
|
||(mem_pc_valid)))
|
||(mem_pc_valid)))
|
upc <= alu_pc;
|
r_upc <= alu_pc;
|
|
assign upc = r_upc;
|
|
`endif
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
ipc <= RESET_ADDRESS;
|
ipc <= RESET_ADDRESS;
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
|
ipc <= wr_spreg_vl[(AW-1):0];
|
ipc <= wr_spreg_vl[(AW-1):0];
|
else if ((~alu_gie)&&
|
else if ((~alu_gie)&&
|
(((alu_pc_valid)&&(~clear_pipeline))
|
(((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal))
|
||(mem_pc_valid)))
|
||(mem_pc_valid)))
|
ipc <= alu_pc;
|
ipc <= alu_pc;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
| Line 1757... |
Line 1882... |
((alu_pc_valid)&&(~clear_pipeline))
|
((alu_pc_valid)&&(~clear_pipeline))
|
||(mem_pc_valid)))
|
||(mem_pc_valid)))
|
pf_pc <= alu_pc;
|
pf_pc <= alu_pc;
|
`endif
|
`endif
|
|
|
initial new_pc = 1'b1;
|
|
always @(posedge i_clk)
|
|
if ((i_rst)||(i_clear_pf_cache))
|
|
new_pc <= 1'b1;
|
|
else if (w_switch_to_interrupt)
|
|
new_pc <= 1'b1;
|
|
else if (w_release_from_interrupt)
|
|
new_pc <= 1'b1;
|
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
|
new_pc <= 1'b1;
|
|
else
|
|
new_pc <= 1'b0;
|
|
|
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
reg r_clear_icache;
|
reg r_clear_icache;
|
initial r_clear_icache = 1'b1;
|
initial r_clear_icache = 1'b1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(i_clear_pf_cache))
|
if ((i_rst)||(i_clear_pf_cache))
|
| Line 1782... |
Line 1894... |
r_clear_icache <= wr_spreg_vl[`CPU_CLRCACHE_BIT];
|
r_clear_icache <= wr_spreg_vl[`CPU_CLRCACHE_BIT];
|
else
|
else
|
r_clear_icache <= 1'b0;
|
r_clear_icache <= 1'b0;
|
assign w_clear_icache = r_clear_icache;
|
assign w_clear_icache = r_clear_icache;
|
`else
|
`else
|
assign w_clear_icache = 1'b0;
|
assign w_clear_icache = i_clear_pf_cache;
|
`endif
|
`endif
|
|
|
|
initial new_pc = 1'b1;
|
|
always @(posedge i_clk)
|
|
if ((i_rst)||(w_clear_icache))
|
|
new_pc <= 1'b1;
|
|
else if (w_switch_to_interrupt)
|
|
new_pc <= 1'b1;
|
|
else if (w_release_from_interrupt)
|
|
new_pc <= 1'b1;
|
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
|
new_pc <= 1'b1;
|
|
else
|
|
new_pc <= 1'b0;
|
|
|
//
|
//
|
// The debug interface
|
// The debug interface
|
|
wire [31:0] w_debug_pc;
|
generate
|
generate
|
|
`ifdef OPT_NO_USERMODE
|
if (AW<32)
|
if (AW<32)
|
begin
|
assign w_debug_pc = {{(32-AW){1'b0}},ipc};
|
|
else
|
|
assign w_debug_pc = ipc;
|
|
`else
|
|
if (AW<32)
|
|
assign w_debug_pc = {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
|
|
else
|
|
assign w_debug_pc = (i_dbg_reg[4])?upc:ipc;
|
|
`endif
|
|
endgenerate
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
o_dbg_reg <= regset[i_dbg_reg];
|
`ifdef OPT_NO_USERMODE
|
|
o_dbg_reg <= regset[i_dbg_reg[3:0]];
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
|
o_dbg_reg <= w_debug_pc;
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
begin
|
begin
|
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
o_dbg_reg[14:0] <= w_iflags;
|
o_dbg_reg[15] <= 1'b0;
|
o_dbg_reg[15] <= 1'b0;
|
o_dbg_reg[31:23] <= w_cpu_info;
|
o_dbg_reg[31:23] <= w_cpu_info;
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
end
|
end
|
end
|
`else
|
end else begin
|
|
always @(posedge i_clk)
|
|
begin
|
|
o_dbg_reg <= regset[i_dbg_reg];
|
o_dbg_reg <= regset[i_dbg_reg];
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
|
o_dbg_reg <= w_debug_pc;
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
begin
|
begin
|
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
o_dbg_reg[15] <= 1'b0;
|
o_dbg_reg[15] <= 1'b0;
|
o_dbg_reg[31:23] <= w_cpu_info;
|
o_dbg_reg[31:23] <= w_cpu_info;
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
end
|
end
|
|
`endif
|
end
|
end
|
end endgenerate
|
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_dbg_cc <= { o_break, bus_err, gie, sleep };
|
o_dbg_cc <= { o_break, bus_err, gie, sleep };
|
|
|
`ifdef OPT_PIPELINED
|
`ifdef OPT_PIPELINED
|
| Line 1906... |
Line 2041... |
|
|
wire [31:0] debug_flags;
|
wire [31:0] debug_flags;
|
assign debug_flags = { debug_trigger, 3'b101,
|
assign debug_flags = { debug_trigger, 3'b101,
|
master_ce, i_halt, o_break, sleep,
|
master_ce, i_halt, o_break, sleep,
|
gie, ibus_err_flag, trap, ill_err_i,
|
gie, ibus_err_flag, trap, ill_err_i,
|
r_clear_icache, pf_valid, pf_illegal, dcd_ce,
|
w_clear_icache, pf_valid, pf_illegal, dcd_ce,
|
dcdvalid, dcd_stalled, op_ce, opvalid,
|
dcdvalid, dcd_stalled, op_ce, opvalid,
|
op_pipe, alu_ce, alu_busy, alu_wr,
|
op_pipe, alu_ce, alu_busy, alu_wr,
|
alu_illegal, alF_wr, mem_ce, mem_we,
|
alu_illegal, alF_wr, mem_ce, mem_we,
|
mem_busy, mem_pipe_stalled, (new_pc), (dcd_early_branch) };
|
mem_busy, mem_pipe_stalled, (new_pc), (dcd_early_branch) };
|
|
|
