| Line 556... |
Line 556... |
`endif
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`endif
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|
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wire ctri_sel, ctri_stall;
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wire ctri_sel, ctri_stall;
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reg ctri_ack;
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reg ctri_ack;
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wire [31:0] ctri_data;
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wire [31:0] ctri_data;
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assign ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
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assign ctri_sel = (sys_stb)&&(sys_addr == `CTRINT);
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always @(posedge i_clk)
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always @(posedge i_clk)
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ctri_ack <= ctri_sel;
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ctri_ack <= ctri_sel;
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assign ctri_stall = 1'b0;
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assign ctri_stall = 1'b0;
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`ifdef INCLUDE_ACCOUNTING_COUNTERS
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`ifdef INCLUDE_ACCOUNTING_COUNTERS
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//
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//
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| Line 660... |
Line 660... |
|
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wire pic_stall;
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wire pic_stall;
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assign pic_stall = 1'b0;
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assign pic_stall = 1'b0;
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reg pic_ack;
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reg pic_ack;
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always @(posedge i_clk)
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always @(posedge i_clk)
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pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL);
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pic_ack <= (sys_stb)&&(sys_addr == `INTCTRL);
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|
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//
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//
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// The CPU itself
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// The CPU itself
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//
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//
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wire cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
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wire cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
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| Line 810... |
Line 810... |
:((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
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:((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
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:((wdbus_ack)?wdbus_data:(ext_idata))));
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:((wdbus_ack)?wdbus_data:(ext_idata))));
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|
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assign sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
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assign sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
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| wdt_stall | ctri_stall | actr_stall
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| wdt_stall | ctri_stall | actr_stall
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| pic_stall | dmac_stall);
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| pic_stall | dmac_stall); // Always 1'b0!
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assign cpu_stall = (sys_stall)|(cpu_ext_stall);
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assign cpu_stall = (sys_stall)|(cpu_ext_stall);
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assign sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|wdbus_ack);
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assign sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|wdbus_ack);
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assign cpu_ack = (sys_ack)||(cpu_ext_ack);
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assign cpu_ack = (sys_ack)||(cpu_ext_ack);
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assign cpu_err = (cpu_ext_err)&&(cpu_gbl_cyc);
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assign cpu_err = (cpu_ext_err)&&(cpu_gbl_cyc);
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|
|
