| Line 168... |
Line 168... |
o_dbg_ack, o_dbg_stall, o_dbg_data
|
o_dbg_ack, o_dbg_stall, o_dbg_data
|
`ifdef DEBUG_SCOPE
|
`ifdef DEBUG_SCOPE
|
, o_cpu_debug
|
, o_cpu_debug
|
`endif
|
`endif
|
);
|
);
|
parameter RESET_ADDRESS=24'h0100000, ADDRESS_WIDTH=24,
|
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
|
LGICACHE=10, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
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LGICACHE=10, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
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`ifdef OPT_MULTIPLY
|
`ifdef OPT_MULTIPLY
|
IMPLEMENT_MPY = `OPT_MULTIPLY,
|
IMPLEMENT_MPY = `OPT_MULTIPLY,
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`else
|
`else
|
IMPLEMENT_MPY = 0,
|
IMPLEMENT_MPY = 0,
|
| Line 316... |
Line 316... |
else if (dbg_cmd_write)
|
else if (dbg_cmd_write)
|
cmd_halt <= ((dbg_idata[10])||(dbg_idata[8]));
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cmd_halt <= ((dbg_idata[10])||(dbg_idata[8]));
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else if ((cmd_step)||(cpu_break))
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else if ((cmd_step)||(cpu_break))
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cmd_halt <= 1'b1;
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cmd_halt <= 1'b1;
|
|
|
initial cmd_clear_pf_cache = 1'b0;
|
initial cmd_clear_pf_cache = 1'b1;
|
always @(posedge i_clk)
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always @(posedge i_clk)
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cmd_clear_pf_cache = (~i_rst)&&(dbg_cmd_write)
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cmd_clear_pf_cache = (~i_rst)&&(dbg_cmd_write)
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&&((dbg_idata[11])||(dbg_idata[6]));
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&&((dbg_idata[11])||(dbg_idata[6]));
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//
|
//
|
initial cmd_step = 1'b0;
|
initial cmd_step = 1'b0;
|
| Line 522... |
Line 522... |
wire dmac_ack, dmac_stall;
|
wire dmac_ack, dmac_stall;
|
wire dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
|
wire dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
|
wire [31:0] dc_data;
|
wire [31:0] dc_data;
|
wire [(AW-1):0] dc_addr;
|
wire [(AW-1):0] dc_addr;
|
wire cpu_gbl_cyc;
|
wire cpu_gbl_cyc;
|
|
wire [31:0] dmac_int_vec;
|
|
assign dmac_int_vec = { 1'b0, alt_int_vector, 1'b0,
|
|
main_int_vector[14:1], 1'b0 };
|
assign dmac_stb = (sys_stb)&&(sys_addr[4]);
|
assign dmac_stb = (sys_stb)&&(sys_addr[4]);
|
`ifdef INCLUDE_DMA_CONTROLLER
|
`ifdef INCLUDE_DMA_CONTROLLER
|
wbdmac #(AW) dma_controller(i_clk, cpu_reset,
|
wbdmac #(AW) dma_controller(i_clk, cpu_reset,
|
sys_cyc, dmac_stb, sys_we,
|
sys_cyc, dmac_stb, sys_we,
|
sys_addr[1:0], sys_data,
|
sys_addr[1:0], sys_data,
|
dmac_ack, dmac_stall, dmac_data,
|
dmac_ack, dmac_stall, dmac_data,
|
// Need the outgoing DMAC wishbone bus
|
// Need the outgoing DMAC wishbone bus
|
dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
|
dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
|
dc_ack, dc_stall, ext_idata, dc_err,
|
dc_ack, dc_stall, ext_idata, dc_err,
|
// External device interrupts
|
// External device interrupts
|
{ 1'b0, alt_int_vector, 1'b0,
|
dmac_int_vec,
|
main_int_vector[14:1], 1'b0 },
|
|
// DMAC interrupt, for upon completion
|
// DMAC interrupt, for upon completion
|
dmac_int);
|
dmac_int);
|
`else
|
`else
|
reg r_dmac_ack;
|
reg r_dmac_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
