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`define ECTRL_READ 3'h3
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`define ECTRL_READ 3'h3
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`define ECTRL_WRITE 3'h4
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`define ECTRL_WRITE 3'h4
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module enetctrl(i_clk, i_rst,
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module enetctrl(i_clk, i_rst,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_mdclk, o_mdio, i_mdio, o_mdwe);
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o_mdclk, o_mdio, i_mdio, o_mdwe,
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o_debug);
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parameter CLKBITS=3; // = 3 for 200MHz source clock, 2 for 100 MHz
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parameter CLKBITS=3; // = 3 for 200MHz source clock, 2 for 100 MHz
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input i_clk, i_rst;
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input i_clk, i_rst;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [4:0] i_wb_addr;
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input [4:0] i_wb_addr;
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input [15:0] i_wb_data;
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input [15:0] i_wb_data;
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//
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//
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input i_mdio;
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input i_mdio;
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output wire o_mdclk;
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output wire o_mdclk;
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output reg o_mdio, o_mdwe;
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output reg o_mdio, o_mdwe;
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//
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//
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output wire [31:0] o_debug;
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//
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parameter PHYADDR = 5'h01;
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parameter PHYADDR = 5'h01;
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reg read_pending, write_pending;
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reg read_pending, write_pending;
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reg [4:0] r_addr;
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reg [4:0] r_addr;
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// Step 2: Generate strobes for when to move, given the clock
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// Step 2: Generate strobes for when to move, given the clock
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reg rclk, zclk;
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reg rclk, zclk;
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initial zclk = 0;
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initial zclk = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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zclk <= &clk_counter;
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zclk <= (&clk_counter[(CLKBITS-1):1])&&(!clk_counter[0]);
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initial rclk = 0;
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initial rclk = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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rclk <= (~clk_counter[(CLKBITS-1)])&&(&clk_counter[(CLKBITS-2):0]);
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rclk <= (~clk_counter[(CLKBITS-1)])&&(&clk_counter[(CLKBITS-2):0]);
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// Step 3: Read from our input port
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// Step 3: Read from our input port
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// Note: I read on the falling edge, he changes on the rising edge
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// Note: I read on the falling edge, he changes on the rising edge
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reg in_idle;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (zclk)
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if (zclk)
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read_reg <= { read_reg[14:0], i_mdio };
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read_reg <= { read_reg[14:0], i_mdio };
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always @(posedge i_clk)
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always @(posedge i_clk)
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zreg_pos <= (reg_pos == 0);
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zreg_pos <= (reg_pos == 0);
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// Note: I change on the falling edge,
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// Note: I change on the falling edge,
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (zclk)
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if (zclk)
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o_mdio <= write_reg[15];
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o_mdio <= write_reg[15];
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reg in_idle;
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initial in_idle = 1'b0;
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initial in_idle = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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in_idle <= (ctrl_state == `ECTRL_IDLE);
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in_idle <= (ctrl_state == `ECTRL_IDLE);
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initial o_wb_stall = 1'b0;
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initial o_wb_stall = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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initial ctrl_state = `ECTRL_RESET;
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initial ctrl_state = `ECTRL_RESET;
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initial write_reg = 16'hffff;
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initial write_reg = 16'hffff;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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if ((zclk)&&(~zreg_pos))
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if ((zclk)&&(!zreg_pos))
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reg_pos <= reg_pos - 1;
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reg_pos <= reg_pos - 1;
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if (zclk)
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if (zclk)
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write_reg <= { write_reg[14:0], 1'b1 };
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write_reg <= { write_reg[14:0], 1'b1 };
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if (i_rst)
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if (i_rst)
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begin // Must go for 167 ms before our 32 clocks
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begin // Must go for 167 ms before our 32 clocks
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end
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end
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`ECTRL_IDLE: begin
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`ECTRL_IDLE: begin
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o_mdwe <= 1'b1; // Write
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o_mdwe <= 1'b1; // Write
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write_reg <= { 4'he, PHYADDR, r_addr, 2'b11 };
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write_reg <= { 4'he, PHYADDR, r_addr, 2'b11 };
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if (write_pending)
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if (write_pending)
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begin
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write_reg[15:12] <= { 4'h5 };
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write_reg[15:12] <= { 4'h5 };
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else if (read_pending)
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write_reg[0] <= 1'b0;
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end else if (read_pending)
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write_reg[15:12] <= { 4'h6 };
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write_reg[15:12] <= { 4'h6 };
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if (read_pending || write_pending)
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if (!zclk)
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begin
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write_reg[15] <= 1'b1;
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reg_pos <= 6'h0f;
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reg_pos <= 6'h0f;
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if ((zclk)&&(read_pending || write_pending))
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begin
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ctrl_state <= `ECTRL_ADDRESS;
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ctrl_state <= `ECTRL_ADDRESS;
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end end
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end end
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`ECTRL_ADDRESS: begin
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`ECTRL_ADDRESS: begin
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o_mdwe <= 1'b1; // Write
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o_mdwe <= 1'b1; // Write
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if ((zreg_pos)&&(zclk))
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if ((zreg_pos)&&(zclk))
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ctrl_state <= `ECTRL_RESET;
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ctrl_state <= `ECTRL_RESET;
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end
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end
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endcase
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endcase
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end
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end
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assign o_debug = {
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o_wb_stall,i_wb_stb,i_wb_we, i_wb_addr, // 8 bits
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o_wb_ack, rclk, o_wb_data[5:0], // 8 bits
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zreg_pos, zclk, reg_pos, // 8 bits
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read_pending, ctrl_state, // 4 bits
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o_mdclk, o_mdwe, o_mdio, i_mdio // 4 bits
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};
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endmodule
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endmodule
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No newline at end of file
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