| Line 47... |
Line 47... |
module enetctrl(i_clk, i_rst,
|
module enetctrl(i_clk, i_rst,
|
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
|
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
|
o_wb_ack, o_wb_stall, o_wb_data,
|
o_wb_ack, o_wb_stall, o_wb_data,
|
o_mdclk, o_mdio, i_mdio, o_mdwe,
|
o_mdclk, o_mdio, i_mdio, o_mdwe,
|
o_debug);
|
o_debug);
|
parameter CLKBITS=3; // = 3 for 200MHz source clock, 2 for 100 MHz
|
parameter CLKBITS=3, // = 3 for 200MHz source clock, 2 for 100 MHz
|
|
PHYADDR = 5'h01;
|
input i_clk, i_rst;
|
input i_clk, i_rst;
|
input i_wb_cyc, i_wb_stb, i_wb_we;
|
input i_wb_cyc, i_wb_stb, i_wb_we;
|
input [4:0] i_wb_addr;
|
input [4:0] i_wb_addr;
|
input [15:0] i_wb_data;
|
input [15:0] i_wb_data;
|
output reg o_wb_ack, o_wb_stall;
|
output reg o_wb_ack, o_wb_stall;
|
| Line 61... |
Line 62... |
output wire o_mdclk;
|
output wire o_mdclk;
|
output reg o_mdio, o_mdwe;
|
output reg o_mdio, o_mdwe;
|
//
|
//
|
output wire [31:0] o_debug;
|
output wire [31:0] o_debug;
|
//
|
//
|
parameter PHYADDR = 5'h01;
|
|
|
|
|
|
reg read_pending, write_pending;
|
reg read_pending, write_pending;
|
reg [4:0] r_addr;
|
reg [4:0] r_addr;
|
reg [15:0] read_reg, write_reg, r_data;
|
reg [15:0] read_reg, write_reg, r_data;
|
reg [2:0] ctrl_state;
|
reg [2:0] ctrl_state;
|
