| Line 209... |
Line 209... |
`ifdef TX_SYNCHRONOUS_WITH_WB_CLK
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`ifdef TX_SYNCHRONOUS_WITH_WB_CLK
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wire tx_busy, tx_complete;
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wire tx_busy, tx_complete;
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`else
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`else
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reg tx_busy, tx_complete;
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reg tx_busy, tx_complete;
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`endif
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`endif
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reg config_hw_crc, config_hw_mac;
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reg config_hw_crc, config_hw_mac, config_hw_ip_check;
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reg rx_crcerr, rx_err, rx_miss, rx_clear;
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reg rx_crcerr, rx_err, rx_miss, rx_clear;
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`ifdef RX_SYNCHRONOUS_WITH_WB_CLK
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`ifdef RX_SYNCHRONOUS_WITH_WB_CLK
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wire rx_valid, rx_busy;
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wire rx_valid, rx_busy;
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`else
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`else
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reg rx_valid, rx_busy;
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reg rx_valid, rx_busy;
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| Line 227... |
Line 227... |
reg p_rx_clear;
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reg p_rx_clear;
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reg [7:0] clear_pipe;
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reg [7:0] clear_pipe;
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|
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initial config_hw_crc = 0;
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initial config_hw_crc = 0;
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initial config_hw_mac = 0;
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initial config_hw_mac = 0;
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initial config_hw_ip_check = 0;
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initial o_net_reset_n = 1'b0;
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initial o_net_reset_n = 1'b0;
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initial tx_cmd = 1'b0;
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initial tx_cmd = 1'b0;
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initial tx_cancel = 1'b0;
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initial tx_cancel = 1'b0;
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initial rx_crcerr = 1'b0;
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initial rx_crcerr = 1'b0;
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initial rx_err = 1'b0;
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initial rx_err = 1'b0;
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| Line 272... |
Line 273... |
pre_cmd <= 1'b0;
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pre_cmd <= 1'b0;
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if ((wr_ctrl)&&(wr_addr==3'b001))
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if ((wr_ctrl)&&(wr_addr==3'b001))
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begin // TX command register
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begin // TX command register
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|
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// Reset bit must be held down to be valid
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// Reset bit must be held down to be valid
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config_hw_ip_check <= (!wr_data[18]);
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o_net_reset_n <= (!wr_data[17]);
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o_net_reset_n <= (!wr_data[17]);
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config_hw_mac <= (!wr_data[16]);
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config_hw_mac <= (!wr_data[16]);
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config_hw_crc <= (!wr_data[15]);
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config_hw_crc <= (!wr_data[15]);
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pre_cmd <= (wr_data[14]);
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pre_cmd <= (wr_data[14]);
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tx_cancel <= (tx_busy)&&(!wr_data[14]);
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tx_cancel <= (tx_busy)&&(!wr_data[14]);
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| Line 303... |
Line 305... |
assign w_maw = MAW+2; // Number of bits in the packet length field
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assign w_maw = MAW+2; // Number of bits in the packet length field
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assign w_rx_ctrl = { 4'h0, w_maw, {(24-19){1'b0}}, rx_crcerr, rx_err,
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assign w_rx_ctrl = { 4'h0, w_maw, {(24-19){1'b0}}, rx_crcerr, rx_err,
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rx_miss, rx_busy, (rx_valid)&&(!rx_clear),
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rx_miss, rx_busy, (rx_valid)&&(!rx_clear),
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{(14-MAW-2){1'b0}}, rx_len };
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{(14-MAW-2){1'b0}}, rx_len };
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|
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assign w_tx_ctrl = { 4'h0, w_maw, {(24-18){1'b0}},
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assign w_tx_ctrl = { 4'h0, w_maw, {(24-19){1'b0}},
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!config_hw_ip_check,
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!o_net_reset_n,!config_hw_mac,
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!o_net_reset_n,!config_hw_mac,
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!config_hw_crc, tx_busy,
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!config_hw_crc, tx_busy,
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{(14-MAW-2){1'b0}}, tx_len };
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{(14-MAW-2){1'b0}}, tx_len };
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|
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reg [31:0] counter_rx_miss, counter_rx_err, counter_rx_crc;
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reg [31:0] counter_rx_miss, counter_rx_err, counter_rx_crc;
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| Line 543... |
Line 546... |
`endif
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`endif
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|
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|
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`ifdef RX_SYNCHRONOUS_WITH_WB_CLK
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`ifdef RX_SYNCHRONOUS_WITH_WB_CLK
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wire n_rx_clear;
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wire n_rx_clear;
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reg n_rx_config_hw_mac, n_rx_config_hw_crc;
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reg n_rx_config_hw_mac, n_rx_config_hw_crc, n_rx_config_ip_check;
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assign n_rx_clear = rx_clear;
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assign n_rx_clear = rx_clear;
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`else
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`else
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(* ASYNC_REG = "TRUE" *) reg n_rx_config_hw_mac, n_rx_config_hw_crc;
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(* ASYNC_REG = "TRUE" *) reg n_rx_config_hw_mac, n_rx_config_hw_crc,
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n_rx_config_ip_check;
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(* ASYNC_REG = "TRUE" *) reg r_rx_clear;
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(* ASYNC_REG = "TRUE" *) reg r_rx_clear;
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reg n_rx_clear;
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reg n_rx_clear;
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always @(posedge `RXCLK)
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always @(posedge `RXCLK)
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begin
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begin
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r_rx_clear <= (p_rx_clear)||(!o_net_reset_n);
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r_rx_clear <= (p_rx_clear)||(!o_net_reset_n);
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| Line 558... |
Line 562... |
end
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end
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`endif
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`endif
|
|
|
|
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reg n_rx_net_err;
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reg n_rx_net_err;
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wire w_npre, w_rxmin, w_rxcrc, w_rxmac, w_rxip;
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wire w_npre, w_rxmin, w_rxcrc, w_rxmac;
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wire [3:0] w_npred, w_rxmind, w_rxcrcd, w_rxmacd, w_rxipd;
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wire [3:0] w_npred, w_rxmind, w_rxcrcd, w_rxmacd;
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wire w_minerr, w_rxcrcerr, w_macerr, w_broadcast, w_iperr;
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wire w_minerr, w_rxcrcerr, w_macerr, w_broadcast, w_iperr;
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`ifndef RX_BYPASS_HW_PREAMBLE
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`ifndef RX_BYPASS_HW_PREAMBLE
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rxepreambl rxprei(`RXCLK, rx_clk_stb, 1'b1, (n_rx_net_err),
|
rxepreambl rxprei(`RXCLK, rx_clk_stb, 1'b1, (n_rx_net_err),
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i_net_dv, i_net_rxd, w_npre, w_npred);
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i_net_dv, i_net_rxd, w_npre, w_npred);
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`else
|
`else
|
assign w_npre = i_net_dv;
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assign w_npre = i_net_dv;
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assign w_npred = i_net_rxerr;
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assign w_npred = i_net_rxerr;
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`endif
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`endif
|
|
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`ifdef RX_HW_MINLENGTH
|
`ifdef RX_BYPASS_HW_MINLENGTH
|
// Insist on a minimum of 64-byte packets
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// Insist on a minimum of 64-byte packets
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rxeminlen rxmini(`RXCLK, rx_clk_stb, 1'b1, (n_rx_net_err),
|
rxemin rxmini(`RXCLK, rx_clk_stb, 1'b1, (n_rx_net_err),
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w_npre, w_npred, w_rxmin, w_rxmind, w_minerr);
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w_npre, w_npred, w_minerr);
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`else
|
`else
|
assign w_rxmin = w_npre;
|
|
assign w_rxmind= w_npred;
|
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assign w_minerr= 1'b0;
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assign w_minerr= 1'b0;
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`endif
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`endif
|
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assign w_rxmin = w_npre;
|
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assign w_rxmind= w_npred;
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|
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`ifndef RX_BYPASS_HW_CRC
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`ifndef RX_BYPASS_HW_CRC
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rxecrc rxcrci(`RXCLK, rx_clk_stb, n_rx_config_hw_crc, (n_rx_net_err),
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rxecrc rxcrci(`RXCLK, rx_clk_stb, n_rx_config_hw_crc, (n_rx_net_err),
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w_rxmin, w_rxmind, w_rxcrc, w_rxcrcd, w_rxcrcerr);
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w_rxmin, w_rxmind, w_rxcrc, w_rxcrcd, w_rxcrcerr);
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`else
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`else
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| Line 598... |
Line 602... |
`else
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`else
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assign w_rxmac = w_rxcrc;
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assign w_rxmac = w_rxcrc;
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assign w_rxmacd = w_rxcrcd;
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assign w_rxmacd = w_rxcrcd;
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`endif
|
`endif
|
|
|
|
`define RX_HW_IPCHECK
|
`ifdef RX_HW_IPCHECK
|
`ifdef RX_HW_IPCHECK
|
// Check: if this packet is an IP packet, is the IP header checksum
|
// Check: if this packet is an IP packet, is the IP header checksum
|
// valid?
|
// valid?
|
|
rxeipchk rxipci(`RXCLK, rx_clk_stb, n_rx_config_ip_check,(n_rx_net_err),
|
|
w_rxcrc, w_rxcrcd, w_iperr);
|
`else
|
`else
|
assign w_rxip = w_rxmac;
|
|
assign w_rxipd = w_rxmacd;
|
|
assign w_iperr = 1'b0;
|
assign w_iperr = 1'b0;
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`endif
|
`endif
|
|
|
wire w_rxwr;
|
wire w_rxwr;
|
wire [(MAW-1):0] w_rxaddr;
|
wire [(MAW-1):0] w_rxaddr;
|
wire [31:0] w_rxdata;
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wire [31:0] w_rxdata;
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wire [(MAW+1):0] w_rxlen;
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wire [(MAW+1):0] w_rxlen;
|
|
|
rxewrite #(MAW) rxememi(`RXCLK, 1'b1, (n_rx_net_err), w_rxip, w_rxipd,
|
rxewrite #(MAW) rxememi(`RXCLK, 1'b1, (n_rx_net_err), w_rxmac, w_rxmacd,
|
w_rxwr, w_rxaddr, w_rxdata, w_rxlen);
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w_rxwr, w_rxaddr, w_rxdata, w_rxlen);
|
|
|
reg last_rxwr, n_rx_valid, n_rxmiss, n_eop, n_rx_busy, n_rx_crcerr,
|
reg last_rxwr, n_rx_valid, n_rxmiss, n_eop, n_rx_busy, n_rx_crcerr,
|
n_rx_err, n_rx_broadcast, n_rx_miss;
|
n_rx_err, n_rx_broadcast, n_rx_miss;
|
reg [(MAW+1):0] n_rx_len;
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reg [(MAW+1):0] n_rx_len;
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| Line 631... |
Line 636... |
|
|
// n_rx_net_err goes true as soon as an error is detected,
|
// n_rx_net_err goes true as soon as an error is detected,
|
// and stays true as long as valid data is coming in
|
// and stays true as long as valid data is coming in
|
n_rx_net_err <= (i_net_dv)&&((i_net_rxerr)||(i_net_col)
|
n_rx_net_err <= (i_net_dv)&&((i_net_rxerr)||(i_net_col)
|
||(w_minerr)||(w_macerr)||(w_rxcrcerr)
|
||(w_minerr)||(w_macerr)||(w_rxcrcerr)
|
|
||(w_iperr)
|
||(n_rx_net_err)
|
||(n_rx_net_err)
|
||((w_rxwr)&&(n_rx_valid)));
|
||((w_rxwr)&&(n_rx_valid)));
|
|
|
last_rxwr <= w_rxwr;
|
last_rxwr <= w_rxwr;
|
n_eop <= (!w_rxwr)&&(last_rxwr)&&(!n_rx_net_err);
|
n_eop <= (!w_rxwr)&&(last_rxwr)&&(!n_rx_net_err);
|
|
|
n_rx_busy <= (!n_rx_net_err)&&((i_net_dv)||(w_npre)||(w_rxmin)
|
n_rx_busy <= (!n_rx_net_err)&&((i_net_dv)||(w_npre)||(w_rxmin)
|
||(w_rxcrc)||(w_rxmac)||(w_rxip)||(w_rxwr));
|
||(w_rxcrc)||(w_rxmac)||(w_rxwr));
|
|
|
// Oops ... we missed a packet
|
// Oops ... we missed a packet
|
n_rx_miss <= (n_rx_valid)&&(w_rxwr)||
|
n_rx_miss <= (n_rx_valid)&&(w_rxwr)||
|
((n_rx_miss)&&(!n_rx_clear));
|
((n_rx_miss)&&(!n_rx_clear));
|
|
|
| Line 667... |
Line 673... |
|
|
if ((!i_net_dv)||(n_rx_clear))
|
if ((!i_net_dv)||(n_rx_clear))
|
begin
|
begin
|
n_rx_config_hw_mac <= config_hw_mac;
|
n_rx_config_hw_mac <= config_hw_mac;
|
n_rx_config_hw_crc <= config_hw_crc;
|
n_rx_config_hw_crc <= config_hw_crc;
|
|
n_rx_config_ip_check <= config_hw_ip_check;
|
end
|
end
|
end
|
end
|
|
|
`ifdef RX_SYNCHRONOUS_WITH_WB_CLK
|
`ifdef RX_SYNCHRONOUS_WITH_WB_CLK
|
assign rx_busy = n_rx_busy;
|
assign rx_busy = n_rx_busy;
|
