| Line 144... |
Line 144... |
`define TXCLK i_wb_clk
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`define TXCLK i_wb_clk
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`else
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`else
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`define TXCLK i_net_tx_clk
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`define TXCLK i_net_tx_clk
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`endif
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`endif
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module enetpackets(i_wb_clk, i_reset,
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module enetpackets(i_wb_clk, i_reset,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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//
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//
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o_net_reset_n,
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o_net_reset_n,
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i_net_rx_clk, i_net_col, i_net_crs, i_net_dv, i_net_rxd, i_net_rxerr,
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i_net_rx_clk, i_net_col, i_net_crs, i_net_dv, i_net_rxd, i_net_rxerr,
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i_net_tx_clk, o_net_tx_en, o_net_txd,
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i_net_tx_clk, o_net_tx_en, o_net_txd,
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| Line 163... |
Line 163... |
input i_wb_clk, i_reset;
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input i_wb_clk, i_reset;
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//
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//
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [(MAW+1):0] i_wb_addr; // 1-bit for ctrl/data, 1 for tx/rx
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input [(MAW+1):0] i_wb_addr; // 1-bit for ctrl/data, 1 for tx/rx
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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input [3:0] i_wb_sel;
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//
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//
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output reg o_wb_ack;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output wire o_wb_stall;
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output reg [31:0] o_wb_data;
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output reg [31:0] o_wb_data;
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//
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//
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| Line 185... |
Line 186... |
output wire [31:0] o_debug;
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output wire [31:0] o_debug;
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|
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reg wr_ctrl;
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reg wr_ctrl;
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reg [2:0] wr_addr;
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reg [2:0] wr_addr;
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reg [31:0] wr_data;
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reg [31:0] wr_data;
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reg [3:0] wr_sel;
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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begin
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begin
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wr_ctrl<=((i_wb_stb)&&(i_wb_we)&&(i_wb_addr[(MAW+1):MAW] == 2'b00));
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wr_ctrl<=((i_wb_stb)&&(i_wb_we)&&(i_wb_addr[(MAW+1):MAW] == 2'b00));
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wr_addr <= i_wb_addr[2:0];
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wr_addr <= i_wb_addr[2:0];
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wr_data <= i_wb_data;
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wr_data <= i_wb_data;
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wr_sel <= i_wb_sel;
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end
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end
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reg [31:0] txmem [0:((1<<MAW)-1)];
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reg [31:0] txmem [0:((1<<MAW)-1)];
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reg [31:0] rxmem [0:((1<<MAW)-1)];
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reg [31:0] rxmem [0:((1<<MAW)-1)];
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| Line 241... |
Line 244... |
initial rx_clear = 1'b0;
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initial rx_clear = 1'b0;
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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begin
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begin
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// if (i_wb_addr[(MAW+1):MAW] == 2'b10)
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// if (i_wb_addr[(MAW+1):MAW] == 2'b10)
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// Writes to rx memory not allowed here
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// Writes to rx memory not allowed here
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if ((i_wb_stb)&&(i_wb_we)&&(i_wb_addr[(MAW+1):MAW] == 2'b11))
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if ((i_wb_stb)&&(i_wb_we)&&(i_wb_addr[(MAW+1):MAW] == 2'b11)
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txmem[i_wb_addr[(MAW-1):0]] <= i_wb_data;
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&&(i_wb_sel[3]))
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txmem[i_wb_addr[(MAW-1):0]][31:24] <= i_wb_data[31:24];
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if ((i_wb_stb)&&(i_wb_we)&&(i_wb_addr[(MAW+1):MAW] == 2'b11)
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&&(i_wb_sel[2]))
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txmem[i_wb_addr[(MAW-1):0]][23:16] <= i_wb_data[23:16];
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if ((i_wb_stb)&&(i_wb_we)&&(i_wb_addr[(MAW+1):MAW] == 2'b11)
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&&(i_wb_sel[1]))
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txmem[i_wb_addr[(MAW-1):0]][15:8] <= i_wb_data[15:8];
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if ((i_wb_stb)&&(i_wb_we)&&(i_wb_addr[(MAW+1):MAW] == 2'b11)
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&&(i_wb_sel[0]))
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txmem[i_wb_addr[(MAW-1):0]][7:0] <= i_wb_data[7:0];
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// Set the err bits on these conditions (filled out below)
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// Set the err bits on these conditions (filled out below)
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if (rx_err_stb)
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if (rx_err_stb)
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rx_err <= 1'b1;
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rx_err <= 1'b1;
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if (rx_miss_stb)
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if (rx_miss_stb)
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