| Line 47... |
Line 47... |
// Wishbone control
|
// Wishbone control
|
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr,
|
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr,
|
i_wb_data, o_wb_ack, o_wb_stall, o_wb_data,
|
i_wb_data, o_wb_ack, o_wb_stall, o_wb_data,
|
// Cross-board I/O
|
// Cross-board I/O
|
i_rtc_ppd, i_buserr, i_other_ints, o_bus_int, o_board_ints);
|
i_rtc_ppd, i_buserr, i_other_ints, o_bus_int, o_board_ints);
|
parameter AUXUART_SETUP = 30'hd50, // 4M baud from 200MHz clock
|
parameter AUXUART_SETUP = 30'd1736, // 115200 baud from 200MHz clk
|
GPSUART_SETUP = 30'hd20833; // 9600 baud from 200MHz clk
|
GPSUART_SETUP = 30'd20833; // 9600 baud from 200MHz clk
|
input i_clk;
|
input i_clk;
|
// Board level I/O
|
// Board level I/O
|
input [3:0] i_sw;
|
input [3:0] i_sw;
|
input [3:0] i_btn;
|
input [3:0] i_btn;
|
output wire [3:0] o_led;
|
output wire [3:0] o_led;
|
| Line 112... |
Line 112... |
gpsrx_int, sd_int, oled_int, zip_int;
|
gpsrx_int, sd_int, oled_int, zip_int;
|
assign { zip_int, oled_int, rtc_int, sd_int,
|
assign { zip_int, oled_int, rtc_int, sd_int,
|
nettx_int, netrx_int, scop_int, flash_int,
|
nettx_int, netrx_int, scop_int, flash_int,
|
pps_int } = i_other_ints;
|
pps_int } = i_other_ints;
|
|
|
|
//
|
|
// The BUS Interrupt controller
|
|
//
|
icontrol #(15) buspic(i_clk, 1'b0,
|
icontrol #(15) buspic(i_clk, 1'b0,
|
(last_wb_stb)&&(last_wb_addr==5'h1),
|
(last_wb_stb)&&(last_wb_addr==5'h1),
|
i_wb_data, pic_data,
|
i_wb_data, pic_data,
|
{ zip_int, oled_int, sd_int,
|
{ zip_int, oled_int, sd_int,
|
gpsrx_int, scop_int, flash_int, gpio_int,
|
gpsrx_int, scop_int, flash_int, gpio_int,
|
| Line 319... |
Line 322... |
//
|
//
|
// The auxilliary UART
|
// The auxilliary UART
|
//
|
//
|
//////
|
//////
|
|
|
// First the receiver
|
//
|
|
// First the Auxilliary UART receiver
|
|
//
|
wire auxrx_stb, auxrx_break, auxrx_perr, auxrx_ferr, auxck_uart;
|
wire auxrx_stb, auxrx_break, auxrx_perr, auxrx_ferr, auxck_uart;
|
wire [7:0] rx_data_aux_port;
|
wire [7:0] rx_data_aux_port;
|
rxuart auxrx(i_clk, 1'b0, aux_setup, i_aux_rx,
|
rxuart auxrx(i_clk, 1'b0, aux_setup, i_aux_rx,
|
auxrx_stb, rx_data_aux_port, auxrx_break,
|
auxrx_stb, rx_data_aux_port, auxrx_break,
|
auxrx_perr, auxrx_ferr, auxck_uart);
|
auxrx_perr, auxrx_ferr, auxck_uart);
|
| Line 337... |
Line 342... |
r_auxrx_data[10] <= auxrx_ferr;
|
r_auxrx_data[10] <= auxrx_ferr;
|
r_auxrx_data[ 9] <= auxrx_perr;
|
r_auxrx_data[ 9] <= auxrx_perr;
|
r_auxrx_data[7:0]<= rx_data_aux_port;
|
r_auxrx_data[7:0]<= rx_data_aux_port;
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if(((i_wb_stb)&&(~i_wb_we)&&(i_wb_addr == 5'h0d))||(auxrx_stb))
|
if(((i_wb_stb)&&(~i_wb_we)&&(i_wb_addr == 5'h0e))||(auxrx_stb))
|
r_auxrx_data[8] <= auxrx_stb;
|
r_auxrx_data[8] <= auxrx_stb;
|
assign o_aux_cts = auxrx_stb;
|
assign o_aux_cts = auxrx_stb;
|
assign auxrx_data = { 20'h00, r_auxrx_data };
|
assign auxrx_data = { 20'h00, r_auxrx_data };
|
assign auxrx_int = r_auxrx_data[8];
|
assign auxrx_int = r_auxrx_data[8];
|
|
|
|
//
|
// Then the transmitter
|
// Then the auxilliary UART transmitter
|
|
//
|
wire auxtx_busy;
|
wire auxtx_busy;
|
reg [7:0] r_auxtx_data;
|
reg [7:0] r_auxtx_data;
|
reg r_auxtx_stb, r_auxtx_break;
|
reg r_auxtx_stb, r_auxtx_break;
|
wire [31:0] auxtx_data;
|
wire [31:0] auxtx_data;
|
txuart auxtx(i_clk, 1'b0, aux_setup,
|
txuart auxtx(i_clk, 1'b0, aux_setup,
|
r_auxtx_break, r_auxtx_stb, r_auxtx_data,
|
r_auxtx_break, r_auxtx_stb, r_auxtx_data,
|
o_aux_tx, auxtx_busy);
|
o_aux_tx, auxtx_busy);
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((last_wb_stb)&&(last_wb_addr == 5'h0e))
|
if ((last_wb_stb)&&(last_wb_addr == 5'h0f))
|
begin
|
begin
|
r_auxtx_stb <= 1'b1;
|
r_auxtx_stb <= 1'b1;
|
r_auxtx_data <= last_wb_data[7:0];
|
r_auxtx_data <= last_wb_data[7:0];
|
r_auxtx_break<= last_wb_data[9];
|
r_auxtx_break<= last_wb_data[9];
|
end else if (~auxtx_busy)
|
end else if (~auxtx_busy)
|
| Line 392... |
Line 398... |
r_gpsrx_data[10] <= gpsrx_ferr;
|
r_gpsrx_data[10] <= gpsrx_ferr;
|
r_gpsrx_data[ 9] <= gpsrx_perr;
|
r_gpsrx_data[ 9] <= gpsrx_perr;
|
r_gpsrx_data[7:0]<= rx_data_gps_port;
|
r_gpsrx_data[7:0]<= rx_data_gps_port;
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if(((i_wb_stb)&&(~i_wb_we)&&(i_wb_addr == 5'h0d))||(gpsrx_stb))
|
if(((i_wb_stb)&&(~i_wb_we)&&(i_wb_addr == 5'h10))||(gpsrx_stb))
|
r_gpsrx_data[8] <= gpsrx_stb;
|
r_gpsrx_data[8] <= gpsrx_stb;
|
assign gpsrx_data = { 20'h00, r_gpsrx_data };
|
assign gpsrx_data = { 20'h00, r_gpsrx_data };
|
assign gpsrx_int = r_gpsrx_data[8];
|
assign gpsrx_int = r_gpsrx_data[8];
|
|
|
|
|
| Line 407... |
Line 413... |
wire [31:0] gpstx_data;
|
wire [31:0] gpstx_data;
|
txuart gpstx(i_clk, 1'b0, gps_setup,
|
txuart gpstx(i_clk, 1'b0, gps_setup,
|
r_gpstx_break, r_gpstx_stb, r_gpstx_data,
|
r_gpstx_break, r_gpstx_stb, r_gpstx_data,
|
o_gps_tx, gpstx_busy);
|
o_gps_tx, gpstx_busy);
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((last_wb_stb)&&(last_wb_addr == 5'h0e))
|
if ((last_wb_stb)&&(last_wb_addr == 5'h11))
|
begin
|
begin
|
r_gpstx_stb <= 1'b1;
|
r_gpstx_stb <= 1'b1;
|
r_gpstx_data <= last_wb_data[7:0];
|
r_gpstx_data <= last_wb_data[7:0];
|
r_gpstx_break<= last_wb_data[9];
|
r_gpstx_break<= last_wb_data[9];
|
end else if (~gpstx_busy)
|
end else if (~gpstx_busy)
|
| Line 436... |
Line 442... |
5'h08: o_wb_data <= w_clr_led0;
|
5'h08: o_wb_data <= w_clr_led0;
|
5'h09: o_wb_data <= w_clr_led1;
|
5'h09: o_wb_data <= w_clr_led1;
|
5'h0a: o_wb_data <= w_clr_led2;
|
5'h0a: o_wb_data <= w_clr_led2;
|
5'h0b: o_wb_data <= w_clr_led3;
|
5'h0b: o_wb_data <= w_clr_led3;
|
5'h0c: o_wb_data <= date_data;
|
5'h0c: o_wb_data <= date_data;
|
5'h0d: o_wb_data <= auxrx_data;
|
// 5'h0d: o_wb_data <= gpio_data;
|
5'h0e: o_wb_data <= auxtx_data;
|
5'h0e: o_wb_data <= auxrx_data;
|
|
5'h0f: o_wb_data <= auxtx_data;
|
5'h10: o_wb_data <= gpsrx_data;
|
5'h10: o_wb_data <= gpsrx_data;
|
5'h11: o_wb_data <= gpstx_data;
|
5'h11: o_wb_data <= gpstx_data;
|
// 5'hf: UART_SETUP
|
// 5'hf: UART_SETUP
|
// 4'h6: GPIO
|
// 4'h6: GPIO
|
// ?? : GPS-UARTRX
|
// ?? : GPS-UARTRX
|
