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//
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//
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// Filename: fastio.v
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// Filename: fastio.v
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//
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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//
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// Purpose:
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// Purpose: This file is used to group all of the simple I/O registers
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// together. These are the I/O registers whose values can be
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// read without requesting it of any submodules, and that are guaranteed
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// not to stall the bus. In general, these are items that can be read
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// or written in one clock (two, if an extra delay is needed to match
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// timing requirements).
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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| Line 157... |
Line 162... |
// read only counter if you will.
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// read only counter if you will.
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reg [31:0] pwr_counter;
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reg [31:0] pwr_counter;
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initial pwr_counter = 32'h00;
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initial pwr_counter = 32'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (pwr_counter[31])
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if (pwr_counter[31])
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pwr_counter[30:0] <= pwr_counter[30:0] + 31'h001;
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pwr_counter[30:0] <= pwr_counter[30:0] + 1'b1;
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else
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else
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pwr_counter[31:0] <= pwr_counter[31:0] + 31'h001;
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pwr_counter[31:0] <= pwr_counter[31:0] + 1'b1;
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//
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// These pwr_counter bits are used for generating a PWM modulated
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// color LED output--allowing us to create multiple different, varied,
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// color LED "colors". Here, we reverse the bits, to make their
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// transitions and PWM that much *less* noticable. (a 50%
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// value, thus, is now an on-off-on-off-etc sequence, vice a
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// sequence of 256 ons followed by a sequence of 256 offs --- it
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// places the transitions into a higher frequency bracket, and costs
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// us no logic to do--only a touch more pain to understand on behalf
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// of the programmer.)
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wire [8:0] rev_pwr_counter;
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assign rev_pwr_counter[8:0] = { pwr_counter[0],
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pwr_counter[1], pwr_counter[2],
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pwr_counter[3], pwr_counter[4],
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pwr_counter[5], pwr_counter[6],
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pwr_counter[7], pwr_counter[8] };
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//
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//
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// BTNSW
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// BTNSW
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//
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//
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// The button and switch control register
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// The button and switch control register
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| Line 267... |
Line 289... |
assign w_clr_led0 = { 5'h0,
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assign w_clr_led0 = { 5'h0,
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r_clr_led0_r[8], r_clr_led0_g[8], r_clr_led0_b[8],
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r_clr_led0_r[8], r_clr_led0_g[8], r_clr_led0_b[8],
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r_clr_led0_r[7:0], r_clr_led0_g[7:0], r_clr_led0_b[7:0]
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r_clr_led0_r[7:0], r_clr_led0_g[7:0], r_clr_led0_b[7:0]
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};
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};
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_clr_led0 <= { (pwr_counter[8:0] < r_clr_led0_r),
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o_clr_led0 <= { (rev_pwr_counter[8:0] < r_clr_led0_r),
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(pwr_counter[8:0] < r_clr_led0_g),
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(rev_pwr_counter[8:0] < r_clr_led0_g),
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(pwr_counter[8:0] < r_clr_led0_b) };
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(rev_pwr_counter[8:0] < r_clr_led0_b) };
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// CLR LED 1
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// CLR LED 1
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wire [31:0] w_clr_led1;
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wire [31:0] w_clr_led1;
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reg [8:0] r_clr_led1_r, r_clr_led1_g, r_clr_led1_b;
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reg [8:0] r_clr_led1_r, r_clr_led1_g, r_clr_led1_b;
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initial r_clr_led1_r = 9'h007;
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initial r_clr_led1_r = 9'h007;
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| Line 289... |
Line 311... |
assign w_clr_led1 = { 5'h0,
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assign w_clr_led1 = { 5'h0,
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r_clr_led1_r[8], r_clr_led1_g[8], r_clr_led1_b[8],
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r_clr_led1_r[8], r_clr_led1_g[8], r_clr_led1_b[8],
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r_clr_led1_r[7:0], r_clr_led1_g[7:0], r_clr_led1_b[7:0]
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r_clr_led1_r[7:0], r_clr_led1_g[7:0], r_clr_led1_b[7:0]
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};
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};
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_clr_led1 <= { (pwr_counter[8:0] < r_clr_led1_r),
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o_clr_led1 <= { (rev_pwr_counter[8:0] < r_clr_led1_r),
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(pwr_counter[8:0] < r_clr_led1_g),
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(rev_pwr_counter[8:0] < r_clr_led1_g),
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(pwr_counter[8:0] < r_clr_led1_b) };
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(rev_pwr_counter[8:0] < r_clr_led1_b) };
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// CLR LED 0
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// CLR LED 0
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wire [31:0] w_clr_led2;
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wire [31:0] w_clr_led2;
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reg [8:0] r_clr_led2_r, r_clr_led2_g, r_clr_led2_b;
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reg [8:0] r_clr_led2_r, r_clr_led2_g, r_clr_led2_b;
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initial r_clr_led2_r = 9'h00f;
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initial r_clr_led2_r = 9'h00f;
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initial r_clr_led2_g = 9'h000;
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initial r_clr_led2_g = 9'h000;
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| Line 310... |
Line 332... |
assign w_clr_led2 = { 5'h0,
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assign w_clr_led2 = { 5'h0,
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r_clr_led2_r[8], r_clr_led2_g[8], r_clr_led2_b[8],
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r_clr_led2_r[8], r_clr_led2_g[8], r_clr_led2_b[8],
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r_clr_led2_r[7:0], r_clr_led2_g[7:0], r_clr_led2_b[7:0]
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r_clr_led2_r[7:0], r_clr_led2_g[7:0], r_clr_led2_b[7:0]
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};
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};
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_clr_led2 <= { (pwr_counter[8:0] < r_clr_led2_r),
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o_clr_led2 <= { (rev_pwr_counter[8:0] < r_clr_led2_r),
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(pwr_counter[8:0] < r_clr_led2_g),
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(rev_pwr_counter[8:0] < r_clr_led2_g),
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(pwr_counter[8:0] < r_clr_led2_b) };
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(rev_pwr_counter[8:0] < r_clr_led2_b) };
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// CLR LED 3
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// CLR LED 3
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wire [31:0] w_clr_led3;
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wire [31:0] w_clr_led3;
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reg [8:0] r_clr_led3_r, r_clr_led3_g, r_clr_led3_b;
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reg [8:0] r_clr_led3_r, r_clr_led3_g, r_clr_led3_b;
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initial r_clr_led3_r = 9'h01f; // LED is on far left
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initial r_clr_led3_r = 9'h01f; // LED is on far left
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initial r_clr_led3_g = 9'h000;
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initial r_clr_led3_g = 9'h000;
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| Line 331... |
Line 353... |
assign w_clr_led3 = { 5'h0,
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assign w_clr_led3 = { 5'h0,
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r_clr_led3_r[8], r_clr_led3_g[8], r_clr_led3_b[8],
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r_clr_led3_r[8], r_clr_led3_g[8], r_clr_led3_b[8],
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r_clr_led3_r[7:0], r_clr_led3_g[7:0], r_clr_led3_b[7:0]
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r_clr_led3_r[7:0], r_clr_led3_g[7:0], r_clr_led3_b[7:0]
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};
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};
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_clr_led3 <= { (pwr_counter[8:0] < r_clr_led3_r),
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o_clr_led3 <= { (rev_pwr_counter[8:0] < r_clr_led3_r),
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(pwr_counter[8:0] < r_clr_led3_g),
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(rev_pwr_counter[8:0] < r_clr_led3_g),
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(pwr_counter[8:0] < r_clr_led3_b) };
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(rev_pwr_counter[8:0] < r_clr_led3_b) };
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//
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//
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// The Calendar DATE
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// The Calendar DATE
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//
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//
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wire [31:0] date_data;
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wire [31:0] date_data;
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| Line 461... |
Line 483... |
assign gpstx_data = { 20'h00,
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assign gpstx_data = { 20'h00,
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gpsck_uart, o_gps_tx, r_gpstx_break, gpstx_busy,
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gpsck_uart, o_gps_tx, r_gpstx_break, gpstx_busy,
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r_gpstx_data };
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r_gpstx_data };
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assign gpstx_int = !gpstx_busy;
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assign gpstx_int = !gpstx_busy;
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reg [32:0] sec_step;
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initial sec_step = 33'h1;
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always @(posedge i_clk)
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if ((w_wb_stb)&&(w_wb_addr == 5'h12))
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sec_step <= { 1'b1, w_wb_data };
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else if (!pps_int)
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sec_step <= 33'h1;
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reg [31:0] time_now_secs;
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initial time_now_secs = 32'h00;
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always @(posedge i_clk)
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if (pps_int)
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time_now_secs <= time_now_secs + sec_step[31:0];
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else if (sec_step[32])
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time_now_secs <= time_now_secs + sec_step[31:0];
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always @(posedge i_clk)
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always @(posedge i_clk)
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case(i_wb_addr)
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case(i_wb_addr)
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5'h00: o_wb_data <= `DATESTAMP;
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5'h00: o_wb_data <= `DATESTAMP;
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5'h01: o_wb_data <= pic_data;
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5'h01: o_wb_data <= pic_data;
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5'h02: o_wb_data <= i_buserr;
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5'h02: o_wb_data <= i_buserr;
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| Line 481... |
Line 519... |
5'h0d: o_wb_data <= gpio_data;
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5'h0d: o_wb_data <= gpio_data;
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5'h0e: o_wb_data <= auxrx_data;
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5'h0e: o_wb_data <= auxrx_data;
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5'h0f: o_wb_data <= auxtx_data;
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5'h0f: o_wb_data <= auxtx_data;
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5'h10: o_wb_data <= gpsrx_data;
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5'h10: o_wb_data <= gpsrx_data;
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5'h11: o_wb_data <= gpstx_data;
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5'h11: o_wb_data <= gpstx_data;
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// 5'h12: o_wb_data <= i_gps_secs;
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5'h12: o_wb_data <= time_now_secs;
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5'h13: o_wb_data <= i_gps_sub;
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5'h13: o_wb_data <= i_gps_sub;
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5'h14: o_wb_data <= i_gps_step;
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5'h14: o_wb_data <= i_gps_step;
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// 5'hf: UART_SETUP
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// 4'h6: GPIO
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// ?? : GPS-UARTRX
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// ?? : GPS-UARTTX
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default: o_wb_data <= 32'h00;
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default: o_wb_data <= 32'h00;
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endcase
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endcase
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assign o_wb_stall = 1'b0;
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assign o_wb_stall = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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