| Line 39... |
Line 39... |
//
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//
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//
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//
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`define NO_ZIP_WBU_DELAY
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`define NO_ZIP_WBU_DELAY
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// `define ZIPCPU
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// `define ZIPCPU
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`ifdef ZIPCPU
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`ifdef ZIPCPU
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//`define ZIP_SYSTEM
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`define ZIP_SYSTEM
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`ifndef ZIP_SYSTEM
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`ifndef ZIP_SYSTEM
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`define ZIP_BONES
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`define ZIP_BONES
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`endif // ZIP_SYSTEM
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`endif // ZIP_SYSTEM
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`endif // ZipCPU
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`endif // ZipCPU
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//
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//
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| Line 60... |
Line 60... |
// `define UART_ACCESS
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// `define UART_ACCESS
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// `define GPS_UART
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// `define GPS_UART
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`define RTC_ACCESS
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`define RTC_ACCESS
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`define OLEDRGB_ACCESS
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`define OLEDRGB_ACCESS
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//
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//
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// `define CPU_SCOPE
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`define FLASH_SCOPE // Position zero
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// `define GPS_SCOPE
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// `define CPU_SCOPE // Position zero
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`define FLASH_SCOPE
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// `define GPS_SCOPE // Position one
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// `define SDRAM_SCOPE
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// `define SDRAM_SCOPE // Position two
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// `define ENET_SCOPE
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// `define ENET_SCOPE
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//
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//
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//
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//
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module fastmaster(i_clk, i_rst,
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module fastmaster(i_clk, i_rst,
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// CNC
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// CNC
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| Line 80... |
Line 80... |
// The Quad SPI Flash
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// The Quad SPI Flash
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o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
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o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
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// The DDR3 SDRAM
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// The DDR3 SDRAM
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o_ddr_reset_n, o_ddr_cke,
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o_ddr_reset_n, o_ddr_cke,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_dqs, o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data,
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o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_oe,
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o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data,
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// The SD Card
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// The SD Card
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o_sd_sck, o_sd_cmd, o_sd_data, i_sd_cmd, i_sd_data, i_sd_detect,
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o_sd_sck, o_sd_cmd, o_sd_data, i_sd_cmd, i_sd_data, i_sd_detect,
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// Ethernet control (MDIO) lines
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// Ethernet control (MDIO) lines
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o_mdclk, o_mdio, o_mdwe, i_mdio,
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o_mdclk, o_mdio, o_mdwe, i_mdio,
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// OLED Control interface (roughly SPI)
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// OLED Control interface (roughly SPI)
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| Line 117... |
Line 118... |
input [3:0] i_qspi_dat;
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input [3:0] i_qspi_dat;
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output wire [1:0] o_qspi_mod;
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output wire [1:0] o_qspi_mod;
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// DDR3 RAM controller
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// DDR3 RAM controller
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output wire o_ddr_reset_n, o_ddr_cke,
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output wire o_ddr_reset_n, o_ddr_cke,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
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output wire [2:0] o_ddr_dqs;
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output wire o_ddr_dqs;
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output wire o_ddr_dm, o_ddr_odt, o_ddr_bus_oe;
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output wire [13:0] o_ddr_addr;
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output wire [13:0] o_ddr_addr;
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output wire [2:0] o_ddr_ba;
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output wire [2:0] o_ddr_ba;
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output wire [31:0] o_ddr_data;
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output wire [31:0] o_ddr_data;
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input [31:0] i_ddr_data;
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input [31:0] i_ddr_data;
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// The SD Card
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// The SD Card
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| Line 619... |
Line 621... |
(!dbg_counter_many[25])|w_led[3],
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(!dbg_counter_many[25])|w_led[3],
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(!dbg_counter_sel[25])|w_led[2],
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(!dbg_counter_sel[25])|w_led[2],
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(!dbg_counter_cyc[25])|w_led[1],
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(!dbg_counter_cyc[25])|w_led[1],
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(!dbg_counter_err[25])|w_led[0] };
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(!dbg_counter_err[25])|w_led[0] };
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*/
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*/
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assign o_led = w_led;
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|
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reg [25:0] dbg_counter_sdram;
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always @(posedge i_clk)
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if ((ram_sel)&&(wb_stb))
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dbg_counter_sdram <= 0;
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else if (wb_stb)
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dbg_counter_sdram[25] <= 1'b1;
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else if (!dbg_counter_sdram[25])
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dbg_counter_sdram <= dbg_counter_sdram+26'h1;
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assign o_led = { w_led[3:1], w_led[0] | (!dbg_counter_sdram[25]) };
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//
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//
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//
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//
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// Real Time Clock (RTC) device level access
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// Real Time Clock (RTC) device level access
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| Line 895... |
Line 906... |
//
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//
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// DDR3-SDRAM
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// DDR3-SDRAM
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//
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//
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//
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//
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`ifdef SDRAM_ACCESS
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`ifdef SDRAM_ACCESS
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wbddrsdram rami(i_clk,
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wbddrsdram #(13,13'd1520) rami(i_clk, i_rst,
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wb_cyc, (wb_stb)&&(ram_sel), wb_we, wb_addr[25:0], wb_data,
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wb_cyc, (wb_stb)&&(ram_sel), wb_we, wb_addr[25:0], wb_data,
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ram_ack, ram_stall, ram_data,
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ram_ack, ram_stall, ram_data,
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o_ddr_reset_n, o_ddr_cke,
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o_ddr_reset_n, o_ddr_cke,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_dqs,
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o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_oe,
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o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
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o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
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`else
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`else
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assign ram_data = 32'h00;
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assign ram_data = 32'h00;
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assign ram_stall = 1'b0;
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assign ram_stall = 1'b0;
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reg r_ram_ack;
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reg r_ram_ack;
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| Line 914... |
Line 925... |
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// And idle the DDR3 SDRAM
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// And idle the DDR3 SDRAM
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assign o_ddr_reset_n = 1'b0; // Leave the SDRAM in reset
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assign o_ddr_reset_n = 1'b0; // Leave the SDRAM in reset
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assign o_ddr_cke = 1'b0; // Disable the SDRAM clock
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assign o_ddr_cke = 1'b0; // Disable the SDRAM clock
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// DQS
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// DQS
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assign o_ddr_dqs = 3'b100; // Leave DQS pins in high impedence
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assign o_ddr_dqs = 1'b0; // Leave DQS pins in high impedence
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// DDR3 control wires (not enabled if CKE=0)
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// DDR3 control wires (not enabled if CKE=0)
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assign o_ddr_cs_n = 1'b0; // NOOP command
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assign o_ddr_cs_n = 1'b1; // Deselect command
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assign o_ddr_ras_n = 1'b1;
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assign o_ddr_ras_n = 1'b1;
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assign o_ddr_cas_n = 1'b1;
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assign o_ddr_cas_n = 1'b1;
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assign o_ddr_we_n = 1'b1;
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assign o_ddr_we_n = 1'b1;
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// (Unused) data wires
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// (Unused) data wires
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assign o_ddr_addr = 14'h00;
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assign o_ddr_addr = 14'h00;
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| Line 1022... |
Line 1033... |
// SCOPE C
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// SCOPE C
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//
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//
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wire [31:0] scop_c_data;
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wire [31:0] scop_c_data;
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wire scop_c_ack, scop_c_stall, scop_c_interrupt;
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wire scop_c_ack, scop_c_stall, scop_c_interrupt;
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//
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//
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//`else
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`ifdef SDRAM_SCOPE
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wire [31:0] scop_sdram_data;
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wire scop_sdram_ack, scop_sdram_stall, scop_sdram_interrupt;
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wire sdram_trigger;
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wire [31:0] sdram_debug;
|
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assign sdram_trigger = (ram_sel)&&(wb_stb);
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assign sdram_debug= {
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o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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(wb_stb)&&(ram_sel), wb_we, ram_stall, ram_ack,
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o_ddr_dqs, o_ddr_dm, o_ddr_bus_oe,
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o_ddr_addr[10], o_ddr_addr[3],
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o_ddr_data[5:0], i_ddr_data[5:0], 8'h00
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};
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|
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wbscope #(5'd12,32,1) ramscope(i_clk, 1'b1, sdram_trigger, sdram_debug,
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// Wishbone interface
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i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)),
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wb_we, wb_addr[0], wb_data,
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scop_sdram_ack, scop_sdram_stall, scop_sdram_data,
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scop_sdram_interrupt);
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|
|
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assign scop_c_ack = scop_sdram_ack;
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assign scop_c_stall = scop_sdram_stall;
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assign scop_c_data = scop_sdram_data;
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assign scop_c_interrupt = scop_sdram_interrupt;
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`else
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assign scop_c_data = 32'h00;
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assign scop_c_data = 32'h00;
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assign scop_c_stall = 1'b0;
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assign scop_c_stall = 1'b0;
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assign scop_c_interrupt = 1'b0;
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assign scop_c_interrupt = 1'b0;
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|
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reg r_scop_c_ack;
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reg r_scop_c_ack;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_scop_c_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b10);
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r_scop_c_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b10);
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assign scop_c_ack = r_scop_c_ack;
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assign scop_c_ack = r_scop_c_ack;
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//`endif
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`endif
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|
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//
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//
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// SCOPE D
|
// SCOPE D
|
//
|
//
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wire [31:0] scop_d_data;
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wire [31:0] scop_d_data;
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