| Line 88... |
Line 88... |
// PMod I/O
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// PMod I/O
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i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
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i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
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// The Quad SPI Flash
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// The Quad SPI Flash
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o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
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o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
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// The DDR3 SDRAM
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// The DDR3 SDRAM
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o_ddr_reset_n, o_ddr_cke,
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o_ddr_reset_n, o_ddr_cke, o_ddr_bus_oe,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_cmd_a, o_ddr_cmd_b, o_ddr_data, i_ddr_data,
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o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_oe,
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o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data,
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// The SD Card
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// The SD Card
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o_sd_sck, o_sd_cmd, o_sd_data, i_sd_cmd, i_sd_data, i_sd_detect,
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o_sd_sck, o_sd_cmd, o_sd_data, i_sd_cmd, i_sd_data, i_sd_detect,
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// Ethernet control (MDIO) lines
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// Ethernet control (MDIO) lines
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o_mdclk, o_mdio, o_mdwe, i_mdio,
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o_mdclk, o_mdio, o_mdwe, i_mdio,
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// OLED Control interface (roughly SPI)
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// OLED Control interface (roughly SPI)
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| Line 126... |
Line 124... |
output wire o_qspi_cs_n, o_qspi_sck;
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output wire o_qspi_cs_n, o_qspi_sck;
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output wire [3:0] o_qspi_dat;
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output wire [3:0] o_qspi_dat;
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input [3:0] i_qspi_dat;
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input [3:0] i_qspi_dat;
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output wire [1:0] o_qspi_mod;
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output wire [1:0] o_qspi_mod;
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// DDR3 RAM controller
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// DDR3 RAM controller
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output wire o_ddr_reset_n, o_ddr_cke,
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output wire o_ddr_reset_n, o_ddr_cke, o_ddr_bus_oe;
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
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output wire [26:0] o_ddr_cmd_a, o_ddr_cmd_b;
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output wire o_ddr_dqs;
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output wire [63:0] o_ddr_data;
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output wire o_ddr_dm, o_ddr_odt, o_ddr_bus_oe;
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input [63:0] i_ddr_data;
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output wire [13:0] o_ddr_addr;
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output wire [2:0] o_ddr_ba;
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output wire [31:0] o_ddr_data;
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input [31:0] i_ddr_data;
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// The SD Card
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// The SD Card
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output wire o_sd_sck;
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output wire o_sd_sck;
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output wire o_sd_cmd;
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output wire o_sd_cmd;
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output wire [3:0] o_sd_data;
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output wire [3:0] o_sd_data;
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input i_sd_cmd;
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input i_sd_cmd;
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| Line 913... |
Line 907... |
//
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//
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// DDR3-SDRAM
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// DDR3-SDRAM
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//
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//
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//
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//
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`ifdef SDRAM_ACCESS
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`ifdef SDRAM_ACCESS
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wire [63:0] w_ram_wide_data;
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wbddrsdram #(13,13'd1520) rami(i_clk, i_rst,
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wbddrsdram #(13,13'd1520) rami(i_clk, i_rst,
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wb_cyc, (wb_stb)&&(ram_sel), wb_we, wb_addr[25:0], wb_data,
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wb_cyc, (wb_stb)&&(ram_sel), wb_we, wb_addr[24:0],
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ram_ack, ram_stall, ram_data,
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{ wb_data, wb_data }, (wb_addr[25])? 8'hf0:8'h0f,
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o_ddr_reset_n, o_ddr_cke,
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ram_ack, ram_stall, w_ram_wide_data,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_reset_n, o_ddr_cke, o_ddr_bus_oe,
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o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_oe,
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o_ddr_cmd_a, o_ddr_cmd_b, o_ddr_data, i_ddr_data);
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o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
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|
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// assign ram_data = (wb_addr[25])?w_ram_wide_data[63:32]:w_ram_wide_data[
|
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assign ram_data = w_ram_wide_data[31:0];
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`else
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`else
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assign ram_data = 32'h00;
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assign ram_data = 32'h00;
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assign ram_stall = 1'b0;
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assign ram_stall = 1'b0;
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reg r_ram_ack;
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reg r_ram_ack;
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always @(posedge i_clk)
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always @(posedge i_clk)
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