| Line 217... |
Line 217... |
// Fast interrupts
|
// Fast interrupts
|
sdcard_int, auxtx_int, auxrx_int, enet_tx_int, enet_rx_int,
|
sdcard_int, auxtx_int, auxrx_int, enet_tx_int, enet_rx_int,
|
gpsrx_int, rtc_pps
|
gpsrx_int, rtc_pps
|
};
|
};
|
|
|
zipsystem #( .RESET_ADDRESS(24'h08000),
|
zipsystem #( .RESET_ADDRESS(24'h0480000),
|
.ADDRESS_WIDTH(ZA),
|
.ADDRESS_WIDTH(ZA),
|
.LGICACHE(10),
|
.LGICACHE(10),
|
.START_HALTED(1),
|
.START_HALTED(0),
|
.EXTERNAL_INTERRUPTS(ZIPINTS),
|
.EXTERNAL_INTERRUPTS(ZIPINTS),
|
.HIGHSPEED_CPU(1))
|
.HIGHSPEED_CPU(0))
|
zippy(i_clk, i_rst,
|
zippy(i_clk, i_rst,
|
// Zippys wishbone interface
|
// Zippys wishbone interface
|
zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
|
zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
|
zip_ack, zip_stall, dwb_idata, zip_err,
|
zip_ack, zip_stall, dwb_idata, zip_err,
|
zip_interrupt_vec, zip_cpu_int,
|
zip_interrupt_vec, zip_cpu_int,
|
| Line 347... |
Line 347... |
assign ram_sel = (skipaddr[4]);
|
assign ram_sel = (skipaddr[4]);
|
assign flash_sel = (skipaddr[4:3]==2'b01);
|
assign flash_sel = (skipaddr[4:3]==2'b01);
|
assign mem_sel = (skipaddr[4:2]==3'b001);
|
assign mem_sel = (skipaddr[4:2]==3'b001);
|
assign netb_sel = (skipaddr[4:1]==4'b0001);
|
assign netb_sel = (skipaddr[4:1]==4'b0001);
|
assign io_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b000);
|
assign io_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b000);
|
assign scop_sel = (~|skipaddr)&&(wb_addr[7:3]==5'b00100);
|
assign scop_sel = (~|skipaddr)&&(wb_addr[7:3]==5'b0010_0);
|
assign rtc_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b001010);
|
assign rtc_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b0010_10);
|
assign sdcard_sel= (~|skipaddr)&&(wb_addr[7:2]==6'b001011);
|
assign sdcard_sel= (~|skipaddr)&&(wb_addr[7:2]==6'b0010_11);
|
assign netp_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b001101);
|
//assign gps_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b0011_00);
|
assign oled_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b001110);
|
assign oled_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b0011_01);
|
assign gps_sel = (~|skipaddr)&&( (wb_addr[7:2]==6'b001100)
|
assign netp_sel = (~|skipaddr)&&(wb_addr[7:3]==5'b0011_1);
|
|| (wb_addr[7:3]==5'b01000));
|
assign gps_sel = (~|skipaddr)&&( (wb_addr[7:2]==6'b0011_00)
|
|
|| (wb_addr[7:3]==5'b0100_0));
|
assign mio_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b101);
|
assign mio_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b101);
|
assign flctl_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b110);
|
assign flctl_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b110);
|
assign cfg_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b111);
|
assign cfg_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b111);
|
|
|
wire skiperr;
|
wire skiperr;
|
| Line 545... |
Line 546... |
wire sel_err; // 5 inputs
|
wire sel_err; // 5 inputs
|
assign sel_err = ( (last_stb)&&(~single_sel_a)&&(~single_sel_b))
|
assign sel_err = ( (last_stb)&&(~single_sel_a)&&(~single_sel_b))
|
||((single_sel_a)&&(single_sel_b))
|
||((single_sel_a)&&(single_sel_b))
|
||((single_sel_a)&&(many_sel_a))
|
||((single_sel_a)&&(many_sel_a))
|
||((single_sel_b)&&(many_sel_b));
|
||((single_sel_b)&&(many_sel_b));
|
assign wb_err = (wb_cyc)&&(sel_err || many_ack || slow_many_ack);
|
assign wb_err = (wb_cyc)&&(sel_err || many_ack || slow_many_ack||ram_err);
|
|
|
|
|
// Finally, if we ever encounter a bus error, knowing the address of
|
// Finally, if we ever encounter a bus error, knowing the address of
|
// the error will be important to figuring out how to fix it. Hence,
|
// the error will be important to figuring out how to fix it. Hence,
|
// we grab it here. Be aware, however, that this might not truly be
|
// we grab it here. Be aware, however, that this might not truly be
|
| Line 621... |
Line 622... |
(!dbg_counter_many[25])|w_led[3],
|
(!dbg_counter_many[25])|w_led[3],
|
(!dbg_counter_sel[25])|w_led[2],
|
(!dbg_counter_sel[25])|w_led[2],
|
(!dbg_counter_cyc[25])|w_led[1],
|
(!dbg_counter_cyc[25])|w_led[1],
|
(!dbg_counter_err[25])|w_led[0] };
|
(!dbg_counter_err[25])|w_led[0] };
|
*/
|
*/
|
|
assign o_led = w_led;
|
reg [25:0] dbg_counter_sdram;
|
|
always @(posedge i_clk)
|
|
if ((ram_sel)&&(wb_stb))
|
|
dbg_counter_sdram <= 0;
|
|
else if (wb_stb)
|
|
dbg_counter_sdram[25] <= 1'b1;
|
|
else if (!dbg_counter_sdram[25])
|
|
dbg_counter_sdram <= dbg_counter_sdram+26'h1;
|
|
assign o_led = { w_led[3:1], w_led[0] | (!dbg_counter_sdram[25]) };
|
|
|
|
|
|
//
|
//
|
//
|
//
|
// Real Time Clock (RTC) device level access
|
// Real Time Clock (RTC) device level access
|
//
|
//
|
//
|
//
|
wire gps_tracking, ck_pps;
|
wire gps_tracking, ck_pps;
|
wire [63:0] gps_step;
|
wire [63:0] gps_step;
|
`ifdef RTC_ACCESS
|
`ifdef RTC_ACCESS
|
rtcgps #(32'h15798f) // 2^48 / 200MHz
|
rtcgps
|
|
// #(32'h15798f) // 2^48 / 200MHz
|
|
#(32'h1a6e3a) // 2^48 / 162.5 MHz
|
thertc(i_clk,
|
thertc(i_clk,
|
wb_cyc, (wb_stb)&&(rtc_sel), wb_we,
|
wb_cyc, (wb_stb)&&(rtc_sel), wb_we,
|
wb_addr[1:0], wb_data,
|
wb_addr[1:0], wb_data,
|
rtc_data, rtc_int, rtc_ppd,
|
rtc_data, rtc_int, rtc_ppd,
|
gps_tracking, ck_pps, gps_step[47:16], rtc_pps);
|
gps_tracking, ck_pps, gps_step[47:16], rtc_pps);
|
| Line 696... |
Line 690... |
//
|
//
|
// OLEDrgb device control
|
// OLEDrgb device control
|
//
|
//
|
//
|
//
|
`ifdef OLEDRGB_ACCESS
|
`ifdef OLEDRGB_ACCESS
|
wboled rgbctrl(i_clk,
|
wboled
|
|
.#( .CBITS(5))// Div ck by 2^5=32, words take 200ns@162.5MHz
|
|
rgbctrl(i_clk,
|
wb_cyc, (wb_stb)&&(oled_sel), wb_we,
|
wb_cyc, (wb_stb)&&(oled_sel), wb_we,
|
wb_addr[1:0], wb_data,
|
wb_addr[1:0], wb_data,
|
oled_ack, oled_stall, oled_data,
|
oled_ack, oled_stall, oled_data,
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
{ o_oled_reset_n, o_oled_vccen, o_oled_pmoden },
|
{ o_oled_reset_n, o_oled_vccen, o_oled_pmoden },
|
| Line 752... |
Line 748... |
wire gps_led;
|
wire gps_led;
|
|
|
//
|
//
|
// GPS CLOCK CONTROL
|
// GPS CLOCK CONTROL
|
//
|
//
|
gpsclock ppsck(i_clk, 1'b0, gps_pps, ck_pps, gps_led,
|
gpsclock #(
|
|
.DEFAULT_STEP(32'h81a6e39b) // 162.5 MHz
|
|
) ppsck(i_clk, 1'b0, gps_pps, ck_pps, gps_led,
|
(wb_stb)&&(gps_sel)&&(~wb_addr[3]),
|
(wb_stb)&&(gps_sel)&&(~wb_addr[3]),
|
wb_we, wb_addr[1:0],
|
wb_we, wb_addr[1:0],
|
wb_data, gck_ack, gck_stall, gck_data,
|
wb_data, gck_ack, gck_stall, gck_data,
|
gps_tracking, gps_now, gps_step, gps_err, gps_locked,
|
gps_tracking, gps_now, gps_step, gps_err, gps_locked,
|
gps_dbg_tick);
|
gps_dbg_tick);
|
| Line 863... |
Line 861... |
//
|
//
|
// RAM MEMORY ACCESS
|
// RAM MEMORY ACCESS
|
//
|
//
|
// There is no option to turn this off--this RAM must always be
|
// There is no option to turn this off--this RAM must always be
|
// present in the design.
|
// present in the design.
|
memdev #(15) // 32kW, or 128kB, 15 address lines
|
memdev #(.AW(15),
|
|
.EXTRACLOCK(1)) // 32kW, or 128kB, 15 address lines
|
blkram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we, wb_addr[14:0],
|
blkram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we, wb_addr[14:0],
|
wb_data, mem_ack, mem_stall, mem_data);
|
wb_data, mem_ack, mem_stall, mem_data);
|
|
|
//
|
//
|
// FLASH MEMORY ACCESS
|
// FLASH MEMORY ACCESS
|
| Line 960... |
Line 959... |
// assign scop_cpu_trigger = zip_scope_data[30];
|
// assign scop_cpu_trigger = zip_scope_data[30];
|
assign scop_cpu_trigger = (wb_stb)&&(mem_sel)&&(~wb_we)
|
assign scop_cpu_trigger = (wb_stb)&&(mem_sel)&&(~wb_we)
|
&&(wb_err)||(zip_scope_data[31]);
|
&&(wb_err)||(zip_scope_data[31]);
|
wbscope #(5'd13) cpuscope(i_clk, 1'b1,(scop_cpu_trigger), zip_scope_data,
|
wbscope #(5'd13) cpuscope(i_clk, 1'b1,(scop_cpu_trigger), zip_scope_data,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)), wb_we, wb_addr[0],
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)),
|
wb_data,
|
wb_we, wb_addr[0], wb_data,
|
scop_cpu_ack, scop_cpu_stall, scop_cpu_data,
|
scop_cpu_ack, scop_cpu_stall, scop_cpu_data,
|
scop_cpu_interrupt);
|
scop_cpu_interrupt);
|
|
|
assign scop_a_data = scop_cpu_data;
|
assign scop_a_data = scop_cpu_data;
|
assign scop_a_ack = scop_cpu_ack;
|
assign scop_a_ack = scop_cpu_ack;
|
| Line 979... |
Line 978... |
// assign scop_cpu_trigger = zip_scope_data[30];
|
// assign scop_cpu_trigger = zip_scope_data[30];
|
assign scop_flash_trigger = (wb_stb)&&((flash_sel)||(flctl_sel));
|
assign scop_flash_trigger = (wb_stb)&&((flash_sel)||(flctl_sel));
|
wbscope #(5'd13) flashscope(i_clk, 1'b1,
|
wbscope #(5'd13) flashscope(i_clk, 1'b1,
|
(scop_flash_trigger), flash_debug,
|
(scop_flash_trigger), flash_debug,
|
// Wishbone interface
|
// Wishbone interface
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)), wb_we, wb_addr[0],
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)),
|
wb_data,
|
wb_we, wb_addr[0], wb_data,
|
scop_flash_ack, scop_flash_stall, scop_flash_data,
|
scop_flash_ack, scop_flash_stall, scop_flash_data,
|
scop_flash_interrupt);
|
scop_flash_interrupt);
|
|
|
assign scop_a_data = scop_flash_data;
|
assign scop_a_data = scop_flash_data;
|
assign scop_a_ack = scop_flash_ack;
|
assign scop_a_ack = scop_flash_ack;
|
| Line 1129... |
Line 1128... |
|
|
// Scopes don't stall, so this line is more formality than anything
|
// Scopes don't stall, so this line is more formality than anything
|
// else.
|
// else.
|
assign scop_stall = ((wb_addr[2:1]==2'b0)?scop_a_stall
|
assign scop_stall = ((wb_addr[2:1]==2'b0)?scop_a_stall
|
: ((wb_addr[2:1]==2'b01)?scop_b_stall
|
: ((wb_addr[2:1]==2'b01)?scop_b_stall
|
: ((wb_addr[2:1]==2'b11)?scop_c_stall
|
: ((wb_addr[2:1]==2'b10)?scop_c_stall
|
: scop_d_stall))); // Will always be 1'b0;
|
: scop_d_stall))); // Will always be 1'b0;
|
initial scop_ack = 1'b0;
|
initial scop_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
scop_ack <= scop_a_ack | scop_b_ack | scop_c_ack | scop_d_ack;
|
scop_ack <= scop_a_ack | scop_b_ack | scop_c_ack | scop_d_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
