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[/] [openarty/] [trunk/] [rtl/] [fasttop.v] - Diff between revs 3 and 12

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Rev 3 Rev 12
Line 106... Line 106... 
                                o_oled_pmoden;
 
                                o_oled_pmoden;
 
        // Aux UART
 
        // Aux UART
 
        input                   i_aux_rx, i_aux_rts;
 
        input                   i_aux_rx, i_aux_rts;
 
        output  wire            o_aux_tx, o_aux_cts;
 
        output  wire            o_aux_tx, o_aux_cts;
 
 
 
 
 
// `define      FULLCLOCK
 
`define FULLCLOCK
 
        // Build our master clock
 
        // Build our master clock
 
        wire    i_clk, clk_for_ddr, clk2_unused, enet_clk, clk5_unused,
 
        wire    i_clk, clk_for_ddr, clk2_unused, enet_clk, clk_analyzer,
 
                clk_feedback, clk_locked;
 
                clk_feedback, clk_locked, clk_analyzer_b;
 
        PLLE2_BASE      #(
 
        PLLE2_BASE      #(
 
                .BANDWIDTH("OPTIMIZED"),        // OPTIMIZED, HIGH, LOW
 
                .BANDWIDTH("OPTIMIZED"),        // OPTIMIZED, HIGH, LOW
 
                .CLKFBOUT_PHASE(0.0),   // Phase offset in degrees of CLKFB, (-360-360)
 
                .CLKFBOUT_PHASE(0.0),   // Phase offset in degrees of CLKFB, (-360-360)
 
                .CLKIN1_PERIOD(10.0),   // Input clock period in ns to ps resolution
 
                .CLKIN1_PERIOD(10.0),   // Input clock period in ns to ps resolution
 
`ifdef  FULLCLOCK
 
`ifdef  FULLCLOCK
 
                // CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: divide amount for each CLKOUT(1-128)
 
                // CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: divide amount for each CLKOUT(1-128)
 
                .CLKFBOUT_MULT(8),      // Multiply value for all CLKOUT (2-64)
 
                .CLKFBOUT_MULT(8),      // Multiply value for all CLKOUT (2-64)
 
                .CLKOUT0_DIVIDE(4),     // 200 MHz
 
                .CLKOUT0_DIVIDE(4),     // 200 MHz
 
                .CLKOUT1_DIVIDE(4),     // 200 MHz
 
                .CLKOUT1_DIVIDE(4),     // 200 MHz clock for DDR memory
 
                .CLKOUT2_DIVIDE(8),     // 100 MHz
 
                .CLKOUT2_DIVIDE(8),     // 100 MHz
 
                .CLKOUT3_DIVIDE(32),    //  25 MHz
 
                .CLKOUT3_DIVIDE(32),    //  25 MHz
 
                .CLKOUT4_DIVIDE(16),    //  50 MHz
 
                .CLKOUT4_DIVIDE(1),     // 800 MHz
 
                .CLKOUT5_DIVIDE(24),
 
                .CLKOUT5_DIVIDE(1),
 
`else
 
`else
 
                // 100*64/40 = 160 -- the fastest speed where the UART will 
                // 100*64/40 = 160 -- the fastest speed where the UART will 
                // still work at 4MBaud.  Others will still support 115200
 
                // still work at 4MBaud.  Others will still support 115200
 
                // Baud
 
                // Baud
 
                // 100*64/36 = 177.78
 
                // 100*64/36 = 177.78
 
                // 100*64/34 = 188.24
 
                // 100*64/34 = 188.24
 
                // 100*64/33 = 193.94
 
                // 100*64/33 = 193.94
 
                .CLKFBOUT_MULT(8),      // Multiply value for all CLKOUT (2-64)
 
                .CLKFBOUT_MULT(8),      // Multiply value for all CLKOUT (2-64)
 
                .CLKOUT0_DIVIDE(5),     // 160 MHz
 
                .CLKOUT0_DIVIDE(5),     // 160 MHz
 
                .CLKOUT1_DIVIDE(5),     // 160 MHz
 
                .CLKOUT1_DIVIDE(5),     // 160 MHz //Clock too slow for DDR mem
 
                .CLKOUT2_DIVIDE(10),    //  80 MHz
 
                .CLKOUT2_DIVIDE(10),    //  80 MHz
 
                .CLKOUT3_DIVIDE(40),    //  20 MHz
 
                .CLKOUT3_DIVIDE(40),    //  20 MHz
 
                .CLKOUT4_DIVIDE(20),    //  40 MHz
 
                .CLKOUT4_DIVIDE(1),     //  40 MHz
 
                .CLKOUT5_DIVIDE(30),
 
                .CLKOUT5_DIVIDE(1),
 
`endif
 
`endif
 
                // CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT
 
                // CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT
 
                .CLKOUT0_DUTY_CYCLE(0.5),
 
                .CLKOUT0_DUTY_CYCLE(0.5),
 
                .CLKOUT1_DUTY_CYCLE(0.5),
 
                .CLKOUT1_DUTY_CYCLE(0.5),
 
                .CLKOUT2_DUTY_CYCLE(0.5),
 
                .CLKOUT2_DUTY_CYCLE(0.5),
 
                .CLKOUT3_DUTY_CYCLE(0.5),
 
                .CLKOUT3_DUTY_CYCLE(0.5),
 
                .CLKOUT4_DUTY_CYCLE(0.5),
 
                .CLKOUT4_DUTY_CYCLE(0.5),
 
                .CLKOUT5_DUTY_CYCLE(0.5),
 
                .CLKOUT5_DUTY_CYCLE(0.5),
 
                // CLKOUT0_PHASE -- phase offset for each CLKOUT
 
                // CLKOUT0_PHASE -- phase offset for each CLKOUT
 
                .CLKOUT0_PHASE(0.0),
 
                .CLKOUT0_PHASE(0.0),
 
                .CLKOUT1_PHASE(90.0),
 
                .CLKOUT1_PHASE(270.0),
 
                .CLKOUT2_PHASE(0.0),
 
                .CLKOUT2_PHASE(0.0),
 
                .CLKOUT3_PHASE(0.0),
 
                .CLKOUT3_PHASE(0.0),
 
                .CLKOUT4_PHASE(0.0),
 
                .CLKOUT4_PHASE(0.0),
 
                .CLKOUT5_PHASE(0.0),
 
                .CLKOUT5_PHASE(180.0),
 
                .DIVCLK_DIVIDE(1),      // Master division value , (1-56)
 
                .DIVCLK_DIVIDE(1),      // Master division value , (1-56)
 
                .REF_JITTER1(0.0),      // Reference input jitter in UI (0.000-0.999)
 
                .REF_JITTER1(0.0),      // Reference input jitter in UI (0.000-0.999)
 
                .STARTUP_WAIT("FALSE")  // Delayu DONE until PLL Locks, ("TRUE"/"FALSE")
 
                .STARTUP_WAIT("FALSE")  // Delayu DONE until PLL Locks, ("TRUE"/"FALSE")
 
        ) genclock(
 
        ) genclock(
 
                // Clock outputs: 1-bit (each) output
 
                // Clock outputs: 1-bit (each) output
 
                .CLKOUT0(i_clk),
 
                .CLKOUT0(i_clk),
 
                .CLKOUT1(clk_for_ddr),
 
                .CLKOUT1(clk_for_ddr),
 
                .CLKOUT2(clk2_unused), // Reserved for flash, should we need it
 
                .CLKOUT2(clk2_unused), // Reserved for flash, should we need it
 
                .CLKOUT3(enet_clk),
 
                .CLKOUT3(enet_clk),
 
                .CLKOUT4(clk4_unused),
 
                .CLKOUT4(clk_analyzer),
 
                .CLKOUT5(clk5_unused),
 
                .CLKOUT5(clk_analyzer_b),
 
                .CLKFBOUT(clk_feedback), // 1-bit output, feedback clock
 
                .CLKFBOUT(clk_feedback), // 1-bit output, feedback clock
 
                .LOCKED(clk_locked),
 
                .LOCKED(clk_locked),
 
                .CLKIN1(i_clk_100mhz),
 
                .CLKIN1(i_clk_100mhz),
 
                .PWRDWN(1'b0),
 
                .PWRDWN(1'b0),
 
                .RST(1'b0),
 
                .RST(1'b0),
Line 218... Line 218... 
        wire    [1:0]    qspi_bmod;
 
        wire    [1:0]    qspi_bmod;
 
        wire    [3:0]    qspi_dat;
 
        wire    [3:0]    qspi_dat;
 
        wire    [3:0]    i_qspi_dat;
 
        wire    [3:0]    i_qspi_dat;
 
 
 
 
 
        //
 
        //
 
        wire    [2:0]    w_ddr_dqs;
 
 
 
        wire    [31:0]   wo_ddr_data, wi_ddr_data;
 
        wire    [31:0]   wo_ddr_data, wi_ddr_data;
 
 
 
        wire            w_ddr_dqs, w_ddr_dm, w_ddr_bus_oe, w_ddr_odt;
 
 
 
        wire    [2:0]    w_ddr_ba;
 
 
 
        wire            w_ddr_cs_n, w_ddr_ras_n, w_ddr_cas_n, w_ddr_we_n;
 
 
 
        wire    [13:0]   w_ddr_addr;
 
 
 
        reg     [31:0]   r_ddr_data;
 
 
 
 
 
        //
 
        //
 
        wire            w_mdio, w_mdwe;
 
        wire            w_mdio, w_mdwe;
 
        //
 
        //
 
        wire            w_sd_cmd;
 
        wire            w_sd_cmd;
 
        wire    [3:0]    w_sd_data;
 
        wire    [3:0]    w_sd_data;
Line 237... Line 242... 
                i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
 
                i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
 
                // Quad SPI flash
 
                // Quad SPI flash
 
                o_qspi_cs_n, w_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
 
                o_qspi_cs_n, w_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
 
                // DDR3 SDRAM
 
                // DDR3 SDRAM
 
                o_ddr_reset_n, o_ddr_cke,
 
                o_ddr_reset_n, o_ddr_cke,
 
                o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
 
                w_ddr_cs_n, w_ddr_ras_n, w_ddr_cas_n, w_ddr_we_n,
 
                w_ddr_dqs, o_ddr_addr, o_ddr_ba, wo_ddr_data, wi_ddr_data,
 
                w_ddr_dqs, w_ddr_dm, w_ddr_odt, w_ddr_bus_oe,
 
 
 
                w_ddr_addr, w_ddr_ba, wo_ddr_data, r_ddr_data,
 
                // SD Card
 
                // SD Card
 
                o_sd_sck, w_sd_cmd, w_sd_data, io_sd_cmd, io_sd, i_sd_cs,
 
                o_sd_sck, w_sd_cmd, w_sd_data, io_sd_cmd, io_sd, i_sd_cs,
 
                // Ethernet control (MDIO) lines
 
                // Ethernet control (MDIO) lines
 
                o_eth_mdclk, w_mdio, w_mdwe, io_eth_mdio,
 
                o_eth_mdclk, w_mdio, w_mdwe, io_eth_mdio,
 
                // OLEDRGB PMod wires
 
                // OLEDRGB PMod wires
Line 270... Line 276... 
        //
 
        //
 
        //      ??      Dual mode in  (not yet)
 
        //      ??      Dual mode in  (not yet)
 
        //      ??      Dual mode out (not yet)
 
        //      ??      Dual mode out (not yet)
 
        //
 
        //
 
        //
 
        //
 
 
 
`define QSPI_OUT_VERSION_ONE
 
 
 
`ifdef  QSPI_OUT_VERSION_ONE
 
        assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
 
        assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
 
                                :((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
 
                                :((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
 
        assign  i_qspi_dat = io_qspi_dat;
 
        assign  i_qspi_dat = io_qspi_dat;
 
        assign  o_qspi_sck = w_qspi_sck;
 
        assign  o_qspi_sck = w_qspi_sck;
 
/*
 
`else
 
        wire    [3:0]   i_qspi_dat_ign;
 
        wire    [3:0]    i_qspi_ignore;
 
        ODDR #(.DDR_CLK_EDGE("OPPOSITE_EDGE"), .INIT(1'b1), .SRTYPE("SYNC"))
 
 
 
                qsck(
 
        xoddr   xqspi_sck( i_clk, { w_qspi_sck,  w_qspi_sck }, o_qspi_sck);
 
                        .Q(o_qspi_sck),
 
        //
 
                        .C(i_clk),
 
        xioddr  xqspi_d0(  i_clk, (~qspi_bmod[0])||(~qspi_bmod[1]),
 
                        .CE(1'b1),
 
                { qspi_dat[0], qspi_dat[0] },
 
                        .D1(w_qspi_sck),
 
                { i_qspi_ignore[0], i_qspi_dat[0] }, io_qspi_dat[0]);
 
                        .D2(w_qspi_sck),
 
        xioddr  xqspi_d1(  i_clk, (qspi_bmod==2'b10),
 
                        .R(1'b0), .S(1'b0));
 
                { qspi_dat[1], qspi_dat[1] },
 
        xioddr  qd0(i_clk, (~qspi_bmod[1])|(~qspi_bmod[0]),
 
                { i_qspi_ignore[1], i_qspi_dat[1] }, io_qspi_dat[1]);
 
                { qspi_dat[0], qspi_dat[0] },
 
        xioddr  xqspi_d2(  i_clk, (qspi_bmod!=2'b11),
 
                { i_qspi_dat[0], i_qspi_dat_ign[0] }, io_qspi_dat[0]);
 
                (qspi_bmod[1])?{ qspi_dat[2], qspi_dat[2] }:2'b11,
 
        xioddr  qd1(i_clk, (qspi_bmod == 2'b10),
 
                { i_qspi_ignore[2], i_qspi_dat[2] }, io_qspi_dat[2]);
 
                { qspi_dat[1], qspi_dat[1] },
 
        xioddr  xqspi_d3(  i_clk, (qspi_bmod!=2'b11),
 
                { i_qspi_dat[1], i_qspi_dat_ign[1] }, io_qspi_dat[1]);
 
                (qspi_bmod[1])?{ qspi_dat[3], qspi_dat[3] }:2'b11,
 
        xioddr  qd2(i_clk, (~qspi_bmod[1])||(~qspi_bmod[0]),
 
                { i_qspi_ignore[3], i_qspi_dat[3] }, io_qspi_dat[3]);
 
                { qspi_dat[2], qspi_dat[2] },
 
`endif
 
                { i_qspi_dat[2], i_qspi_dat_ign[2] }, io_qspi_dat[2]);
 
 
 
        xioddr  qd3(i_clk, (~qspi_bmod[1])||(~qspi_bmod[0]),
 
 
 
                { qspi_dat[3], qspi_dat[3] },
 
 
 
                { i_qspi_dat[3], i_qspi_dat_ign[3] }, io_qspi_dat[3]);
 
 
 
*/
 
 
 
 
 
 
 
        //
 
        //
 
        // Proposed QSPI mode select, to allow dual I/O mode
 
        // Proposed QSPI mode select, to allow dual I/O mode
 
        //      000     Normal SPI mode
 
        //      000     Normal SPI mode
 
        //      001     Dual mode input
 
        //      001     Dual mode input
Line 314... Line 317... 
        // assign io_qspi_dat[1] = (~qspi_bmod[1])?qspi_dat[1]:1'bz;
 
        // assign io_qspi_dat[1] = (~qspi_bmod[1])?qspi_dat[1]:1'bz;
 
        // assign io_qspi_dat[0] = (qspi_bmod[0])?1'bz : qspi_dat[0];
 
        // assign io_qspi_dat[0] = (qspi_bmod[0])?1'bz : qspi_dat[0];
 
 
 
 
 
        //
 
        //
 
        //
 
        //
 
        // The following primitive is necessary in order to gain access
 
        // The following primitive is necessary on other boards in order to
 
        // to the o_qspi_sck pin.  
        // gain access to the o_qspi_sck pin.  On the Arty, however, there is
 
 
 
        // a clock PIN, so we don't need this primitive.
 
        //
 
        //
 
        //
 
        //
 
/*
 
/*
 
        wire    [3:0]   su_nc;  // Startup primitive, no connect
 
        wire    [3:0]   su_nc;  // Startup primitive, no connect
 
        STARTUPE2 #(
 
        STARTUPE2 #(
Line 385... Line 389... 
        assign io_sd_cmd = w_sd_cmd ? 1'bz:1'b0;
 
        assign io_sd_cmd = w_sd_cmd ? 1'bz:1'b0;
 
        assign io_sd[0] = w_sd_data[0]? 1'bz:1'b0;
 
        assign io_sd[0] = w_sd_data[0]? 1'bz:1'b0;
 
        assign io_sd[1] = w_sd_data[1]? 1'bz:1'b0;
 
        assign io_sd[1] = w_sd_data[1]? 1'bz:1'b0;
 
        assign io_sd[2] = w_sd_data[2]? 1'bz:1'b0;
 
        assign io_sd[2] = w_sd_data[2]? 1'bz:1'b0;
 
        assign io_sd[3] = w_sd_data[3]? 1'bz:1'b0;
 
        assign io_sd[3] = w_sd_data[3]? 1'bz:1'b0;
 
        assign  o_sd_wp = 1'b0;
 
 
 
 
 
 
 
 
 
 
 
        //
 
        //
 
        //
 
        //
 
        // Wire(s) for setting up the MDIO ethernet control structure
 
        // Wire(s) for setting up the MDIO ethernet control structure
Line 400... Line 403... 
        //
 
        //
 
        //
 
        //
 
        // Wires for setting up the DDR3 memory
 
        // Wires for setting up the DDR3 memory
 
        //
 
        //
 
        //
 
        //
 
        wire    [31:0]   r_ddr_data;
 
`ifdef  SDRAM_ACCESS
 
 
 
        reg     [15:0]   bottom_half_data;
 
        xioddr  p0(i_clk, ~o_ddr_we_n, { wo_ddr_data[16], wo_ddr_data[0] },
 
        always @(posedge i_clk)
 
 
 
                bottom_half_data <= wo_ddr_data[15:0];
 
 
 
        xioddr  p0(i_clk, w_ddr_bus_oe, { wo_ddr_data[16], wo_ddr_data[0] },
 
                { wi_ddr_data[16], wi_ddr_data[0] }, io_ddr_data[0]);
 
                { wi_ddr_data[16], wi_ddr_data[0] }, io_ddr_data[0]);
 
 
 
 
 
        xioddr  p1(i_clk, ~o_ddr_we_n, { wo_ddr_data[17], wo_ddr_data[1] },
 
        xioddr  p1(i_clk, w_ddr_bus_oe, { wo_ddr_data[17], wo_ddr_data[1] },
 
                { wi_ddr_data[17], wi_ddr_data[1] }, io_ddr_data[1]);
 
                { wi_ddr_data[17], wi_ddr_data[1] }, io_ddr_data[1]);
 
 
 
 
 
        xioddr  p2(i_clk, ~o_ddr_we_n, { wo_ddr_data[18], wo_ddr_data[2] },
 
        xioddr  p2(i_clk, w_ddr_bus_oe, { wo_ddr_data[18], wo_ddr_data[2] },
 
                { wi_ddr_data[18], wi_ddr_data[2] }, io_ddr_data[2]);
 
                { wi_ddr_data[18], wi_ddr_data[2] }, io_ddr_data[2]);
 
 
 
 
 
        xioddr  p3(i_clk, ~o_ddr_we_n, { wo_ddr_data[19], wo_ddr_data[3] },
 
        xioddr  p3(i_clk, w_ddr_bus_oe, { wo_ddr_data[19], wo_ddr_data[3] },
 
                { wi_ddr_data[19], wi_ddr_data[3] }, io_ddr_data[3]);
 
                { wi_ddr_data[19], wi_ddr_data[3] }, io_ddr_data[3]);
 
 
 
 
 
        xioddr  p4(i_clk, ~o_ddr_we_n, { wo_ddr_data[20], wo_ddr_data[4] },
 
        xioddr  p4(i_clk, w_ddr_bus_oe, { wo_ddr_data[20], wo_ddr_data[4] },
 
                { wi_ddr_data[20], wi_ddr_data[4] }, io_ddr_data[4]);
 
                { wi_ddr_data[20], wi_ddr_data[4] }, io_ddr_data[4]);
 
 
 
 
 
        xioddr  p5(i_clk, ~o_ddr_we_n, { wo_ddr_data[21], wo_ddr_data[5] },
 
        xioddr  p5(i_clk, w_ddr_bus_oe, { wo_ddr_data[21], wo_ddr_data[5] },
 
                { wi_ddr_data[21], wi_ddr_data[5] }, io_ddr_data[5]);
 
                { wi_ddr_data[21], wi_ddr_data[5] }, io_ddr_data[5]);
 
 
 
 
 
        xioddr  p6(i_clk, ~o_ddr_we_n, { wo_ddr_data[22], wo_ddr_data[6] },
 
        xioddr  p6(i_clk, w_ddr_bus_oe, { wo_ddr_data[22], wo_ddr_data[6] },
 
                { wi_ddr_data[22], wi_ddr_data[6] }, io_ddr_data[6]);
 
                { wi_ddr_data[22], wi_ddr_data[6] }, io_ddr_data[6]);
 
 
 
 
 
        xioddr  p7(i_clk, ~o_ddr_we_n, { wo_ddr_data[23], wo_ddr_data[7] },
 
        xioddr  p7(i_clk, w_ddr_bus_oe, { wo_ddr_data[23], wo_ddr_data[7] },
 
                { wi_ddr_data[23], wi_ddr_data[7] }, io_ddr_data[7]);
 
                { wi_ddr_data[23], wi_ddr_data[7] }, io_ddr_data[7]);
 
 
 
 
 
        xioddr  p8(i_clk, ~o_ddr_we_n, { wo_ddr_data[24], wo_ddr_data[8] },
 
        xioddr  p8(i_clk, w_ddr_bus_oe, { wo_ddr_data[24], wo_ddr_data[8] },
 
                { wi_ddr_data[24], wi_ddr_data[8] }, io_ddr_data[8]);
 
                { wi_ddr_data[24], wi_ddr_data[8] }, io_ddr_data[8]);
 
 
 
 
 
        xioddr  p9(i_clk, ~o_ddr_we_n, { wo_ddr_data[25], wo_ddr_data[9] },
 
        xioddr  p9(i_clk, w_ddr_bus_oe, { wo_ddr_data[25], wo_ddr_data[9] },
 
                { wi_ddr_data[25], wi_ddr_data[9] }, io_ddr_data[9]);
 
                { wi_ddr_data[25], wi_ddr_data[9] }, io_ddr_data[9]);
 
 
 
 
 
        xioddr  pa(i_clk, ~o_ddr_we_n, { wo_ddr_data[26], wo_ddr_data[10] },
 
        xioddr  pa(i_clk, w_ddr_bus_oe, { wo_ddr_data[26], wo_ddr_data[10] },
 
                { wi_ddr_data[26], wi_ddr_data[10] }, io_ddr_data[10]);
 
                { wi_ddr_data[26], wi_ddr_data[10] }, io_ddr_data[10]);
 
 
 
 
 
        xioddr  pb(i_clk, ~o_ddr_we_n, { wo_ddr_data[27], wo_ddr_data[11] },
 
        xioddr  pb(i_clk, w_ddr_bus_oe, { wo_ddr_data[27], wo_ddr_data[11] },
 
                { wi_ddr_data[27], wi_ddr_data[11] }, io_ddr_data[11]);
 
                { wi_ddr_data[27], wi_ddr_data[11] }, io_ddr_data[11]);
 
 
 
 
 
        xioddr  pc(i_clk, ~o_ddr_we_n, { wo_ddr_data[28], wo_ddr_data[12] },
 
        xioddr  pc(i_clk, w_ddr_bus_oe, { wo_ddr_data[28], wo_ddr_data[12] },
 
                { wi_ddr_data[28], wi_ddr_data[12] }, io_ddr_data[12]);
 
                { wi_ddr_data[28], wi_ddr_data[12] }, io_ddr_data[12]);
 
 
 
 
 
        xioddr  pd(i_clk, ~o_ddr_we_n, { wo_ddr_data[29], wo_ddr_data[13] },
 
        xioddr  pd(i_clk, w_ddr_bus_oe, { wo_ddr_data[29], wo_ddr_data[13] },
 
                { wi_ddr_data[29], wi_ddr_data[13] }, io_ddr_data[13]);
 
                { wi_ddr_data[29], wi_ddr_data[13] }, io_ddr_data[13]);
 
 
 
 
 
        xioddr  pe(i_clk, ~o_ddr_we_n, { wo_ddr_data[30], wo_ddr_data[14] },
 
        xioddr  pe(i_clk, w_ddr_bus_oe, { wo_ddr_data[30], wo_ddr_data[14] },
 
                { wi_ddr_data[30], wi_ddr_data[14] }, io_ddr_data[14]);
 
                { wi_ddr_data[30], wi_ddr_data[14] }, io_ddr_data[14]);
 
 
 
 
 
        xioddr  pf(i_clk, ~o_ddr_we_n, { wo_ddr_data[31], wo_ddr_data[15] },
 
        xioddr  pf(i_clk, w_ddr_bus_oe, { wo_ddr_data[31], wo_ddr_data[15] },
 
                { wi_ddr_data[31], wi_ddr_data[15] }, io_ddr_data[15]);
 
                { wi_ddr_data[31], wi_ddr_data[15] }, io_ddr_data[15]);
 
 
 
        always @(posedge i_clk)
 
 
 
                r_ddr_data <= wi_ddr_data;
 
 
 
 
 
        OBUFTDS #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
 
        wire    [7:0]    w_dqs_ignore;
 
                dqsbuf0(.O(io_ddr_dqs_p[0]), .OB(io_ddr_dqs_n[0]),
 
        xioddrds        dqs0(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
 
                        .I(w_ddr_dqs[1]), .T(w_ddr_dqs[2]));
 
                { w_dqs_ignore[0], w_dqs_ignore[1] },
 
        OBUFTDS #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
 
                io_ddr_dqs_p[0], io_ddr_dqs_n[0]);
 
                dqsbuf1(.O(io_ddr_dqs_p[1]), .OB(io_ddr_dqs_n[1]),
 
        xioddrds        dqs1(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
 
                        .I(w_ddr_dqs[0]), .T(w_ddr_dqs[2]));
 
                { w_dqs_ignore[2], w_dqs_ignore[3] },
 
 
 
                io_ddr_dqs_p[1], io_ddr_dqs_n[1]);
 
 
 
 
 
 
 
        xoddr   xcs_n( i_clk, { w_ddr_cs_n,  w_ddr_cs_n  }, o_ddr_cs_n);
 
 
 
        xoddr   xras_n(i_clk, { w_ddr_ras_n, w_ddr_ras_n }, o_ddr_ras_n);
 
 
 
        xoddr   xcas_n(i_clk, { w_ddr_cas_n, w_ddr_cas_n }, o_ddr_cas_n);
 
 
 
        xoddr   xwe_n( i_clk, { w_ddr_we_n,  w_ddr_we_n  }, o_ddr_we_n);
 
 
 
        xoddr   xba0(  i_clk, { w_ddr_ba[0], w_ddr_ba[0]  }, o_ddr_ba[0]);
 
 
 
        xoddr   xba1(  i_clk, { w_ddr_ba[1], w_ddr_ba[1]  }, o_ddr_ba[1]);
 
 
 
        xoddr   xba2(  i_clk, { w_ddr_ba[2], w_ddr_ba[2]  }, o_ddr_ba[2]);
 
 
 
        xoddr   xaddr0(i_clk, { w_ddr_addr[0], w_ddr_addr[0] }, o_ddr_addr[0]);
 
 
 
        xoddr   xaddr1(i_clk, { w_ddr_addr[1], w_ddr_addr[1] }, o_ddr_addr[1]);
 
 
 
        xoddr   xaddr2(i_clk, { w_ddr_addr[2], w_ddr_addr[2] }, o_ddr_addr[2]);
 
 
 
        xoddr   xaddr3(i_clk, { w_ddr_addr[3], w_ddr_addr[3] }, o_ddr_addr[3]);
 
 
 
        xoddr   xaddr4(i_clk, { w_ddr_addr[4], w_ddr_addr[4] }, o_ddr_addr[4]);
 
 
 
        xoddr   xaddr5(i_clk, { w_ddr_addr[5], w_ddr_addr[5] }, o_ddr_addr[5]);
 
 
 
        xoddr   xaddr6(i_clk, { w_ddr_addr[6], w_ddr_addr[6] }, o_ddr_addr[6]);
 
 
 
        xoddr   xaddr7(i_clk, { w_ddr_addr[7], w_ddr_addr[7] }, o_ddr_addr[7]);
 
 
 
        xoddr   xaddr8(i_clk, { w_ddr_addr[8], w_ddr_addr[8] }, o_ddr_addr[8]);
 
 
 
        xoddr   xaddr9(i_clk, { w_ddr_addr[9], w_ddr_addr[9] }, o_ddr_addr[9]);
 
 
 
        xoddr   xaddr10(i_clk,{ w_ddr_addr[10],w_ddr_addr[10]}, o_ddr_addr[10]);
 
 
 
        xoddr   xaddr11(i_clk,{ w_ddr_addr[11],w_ddr_addr[11]}, o_ddr_addr[11]);
 
 
 
        xoddr   xaddr12(i_clk,{ w_ddr_addr[12],w_ddr_addr[12]}, o_ddr_addr[12]);
 
 
 
        xoddr   xaddr13(i_clk,{ w_ddr_addr[13],w_ddr_addr[13]}, o_ddr_addr[13]);
 
 
 
 
 
 
 
        wire    w_clk_for_ddr;
 
 
 
        ODDR    #(.DDR_CLK_EDGE("SAME_EDGE"))
 
 
 
                memclkddr(.Q(w_clk_for_ddr), .C(clk_for_ddr), .CE(1'b1),
 
 
 
                        .D1(1'b0), .D2(1'b1), .R(1'b0), .S(1'b0));
 
        OBUFDS  #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
 
        OBUFDS  #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
 
                clkbuf(.O(o_ddr_ck_p), .OB(o_ddr_ck_n), .I(clk_for_ddr));
 
                clkbuf(.O(o_ddr_ck_p), .OB(o_ddr_ck_n), .I(w_clk_for_ddr));
 
 
 
 
 
        assign  o_ddr_dm  = 2'b00;
 
        // assign       o_ddr_dm[0] = w_ddr_dm;
 
 
 
        // assign       o_ddr_dm[1] = w_ddr_dm;
 
 
 
        xoddr   xdm0(i_clk,{ w_ddr_dm, w_ddr_dm }, o_ddr_dm[0]);
 
 
 
        xoddr   xdm1(i_clk,{ w_ddr_dm, w_ddr_dm }, o_ddr_dm[1]);
 
 
 
 
 
 
 
        assign  o_ddr_odt = (~o_ddr_reset_n)? 1'bz : w_ddr_odt;
 
 
 
 
 
 
 
        // xlogicanalyzer ladata(i_clk, io_ddr_data[0], w_ddr_debug[3:0]);
 
 
 
        // xlogicanalyzer ladclk(clk_analyzer, clk_analyzer_b,
 
 
 
                // i_clk, o_ddr_ck_p, w_ddr_debug[7:4]);
 
 
 
        assign w_ddr_debug[7:4] = 4'h0;
 
 
 
        assign w_ddr_debug[3:0] = 4'h0;
 
 
 
`else
 
 
 
        assign  o_ddr_cs_n = w_ddr_cs_n;
 
 
 
        assign  o_ddr_ras_n = w_ddr_ras_n;
 
 
 
        assign  o_ddr_cas_n = w_ddr_cas_n;
 
 
 
        assign  o_ddr_we_n = w_ddr_we_n;
 
 
 
        //
 
 
 
        assign  o_ddr_ba = w_ddr_ba;
 
 
 
        assign  o_ddr_addr = w_ddr_addr;
 
 
 
        //
 
 
 
        assign  o_ddr_dm[1:0] = 2'b00;
 
        assign  o_ddr_odt = 1'b0;
 
        assign  o_ddr_odt = 1'b0;
 
 
 
        //
 
 
 
        assign  io_ddr_data = 16'bzzzz_zzzz_zzzz_zzzz;
 
 
 
        always @(posedge i_clk)
 
 
 
                r_ddr_data = 16'h0000;
 
 
 
 
 
 
 
        //wire  w_clk_for_ddr;
 
 
 
        //ODDR  #(.DDR_CLK_EDGE("SAME_EDGE"))
 
 
 
                //memclkddr(.Q(w_clk_for_ddr), .C(clk_for_ddr), .CE(1'b1),
 
 
 
                        //.D1(1'b0), .D2(1'b1), .R(1'b0), .S(1'b0));
 
 
 
        OBUFDS  #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
 
 
 
                clkbuf(.O(o_ddr_ck_p), .OB(o_ddr_ck_n), .I(1'b1));
 
 
 
 
 
 
 
        wire    [7:0]    w_dqs_ignore;
 
 
 
        xioddrds        dqs0(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
 
 
 
                { w_dqs_ignore[0], w_dqs_ignore[1] },
 
 
 
                io_ddr_dqs_p[0], io_ddr_dqs_n[0]);
 
 
 
        xioddrds        dqs1(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
 
 
 
                { w_dqs_ignore[2], w_dqs_ignore[3] },
 
 
 
                io_ddr_dqs_p[1], io_ddr_dqs_n[1]);
 
 
 
 
 
 
 
 
 
 
 
`endif
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
 
 
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