| Line 108... |
Line 108... |
input i_aux_rx, i_aux_rts;
|
input i_aux_rx, i_aux_rts;
|
output wire o_aux_tx, o_aux_cts;
|
output wire o_aux_tx, o_aux_cts;
|
|
|
`define FULLCLOCK
|
`define FULLCLOCK
|
// Build our master clock
|
// Build our master clock
|
wire i_clk, clk_for_ddr, clk2_unused, enet_clk, clk_analyzer,
|
wire i_clk, clk_for_ddr, mem_serial_clk, mem_serial_clk_inv,
|
clk_feedback, clk_locked, clk_analyzer_b;
|
enet_clk, clk_halfspeed, clk_feedback, clk_locked, clk_unused;
|
PLLE2_BASE #(
|
PLLE2_BASE #(
|
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
|
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
|
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360-360)
|
.CLKFBOUT_PHASE(0.0), // Phase off. in deg of CLKFB,(-360-360)
|
.CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution
|
.CLKIN1_PERIOD(10.0), // Input clock period in ns resolution
|
`ifdef FULLCLOCK
|
`ifdef FULLCLOCK
|
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: divide amount for each CLKOUT(1-128)
|
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE:
|
|
// divide amount for each CLKOUT(1-128)
|
.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
|
.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
|
.CLKOUT0_DIVIDE(4), // 200 MHz
|
.CLKOUT0_DIVIDE(4), // 200 MHz
|
.CLKOUT1_DIVIDE(4), // 200 MHz clock for DDR memory
|
.CLKOUT1_DIVIDE(1), // 800 MHz clock for DDR memory
|
.CLKOUT2_DIVIDE(8), // 100 MHz
|
.CLKOUT2_DIVIDE(1), // 800 MHz clock to run DDR I/O
|
.CLKOUT3_DIVIDE(32), // 25 MHz
|
.CLKOUT3_DIVIDE(1), // 800MHz clk inv to run DDR I/O
|
.CLKOUT4_DIVIDE(1), // 800 MHz
|
.CLKOUT4_DIVIDE(8), // 100 MHz
|
.CLKOUT5_DIVIDE(1),
|
.CLKOUT5_DIVIDE(32), // 25 MHz
|
`else
|
`else
|
// 100*64/40 = 160 -- the fastest speed where the UART will
|
// 100*64/40 = 160 -- the fastest speed where the UART will
|
// still work at 4MBaud. Others will still support 115200
|
// still work at 4MBaud. Others will still support 115200
|
// Baud
|
// Baud
|
// 100*64/36 = 177.78
|
// 100*64/36 = 177.78
|
// 100*64/34 = 188.24
|
// 100*64/34 = 188.24
|
// 100*64/33 = 193.94
|
// 100*64/33 = 193.94
|
.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
|
.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
|
.CLKOUT0_DIVIDE(5), // 160 MHz
|
.CLKOUT0_DIVIDE(5), // 160 MHz
|
.CLKOUT1_DIVIDE(5), // 160 MHz //Clock too slow for DDR mem
|
.CLKOUT1_DIVIDE(5), // 160 MHz //Clock too slow for DDR mem
|
.CLKOUT2_DIVIDE(10), // 80 MHz
|
.CLKOUT2_DIVIDE(5), // 160 MHz // Clock too slow for DDR
|
.CLKOUT3_DIVIDE(40), // 20 MHz
|
.CLKOUT3_DIVIDE(5), // 160 MHz // Clock too slow for DDR
|
.CLKOUT4_DIVIDE(1), // 40 MHz
|
.CLKOUT4_DIVIDE(20), // 40 MHz
|
.CLKOUT5_DIVIDE(1),
|
.CLKOUT5_DIVIDE(5),
|
`endif
|
`endif
|
// CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT
|
// CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
| Line 149... |
Line 150... |
.CLKOUT5_DUTY_CYCLE(0.5),
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
// CLKOUT0_PHASE -- phase offset for each CLKOUT
|
// CLKOUT0_PHASE -- phase offset for each CLKOUT
|
.CLKOUT0_PHASE(0.0),
|
.CLKOUT0_PHASE(0.0),
|
.CLKOUT1_PHASE(270.0),
|
.CLKOUT1_PHASE(270.0),
|
.CLKOUT2_PHASE(0.0),
|
.CLKOUT2_PHASE(0.0),
|
.CLKOUT3_PHASE(0.0),
|
.CLKOUT3_PHASE(180.0),
|
.CLKOUT4_PHASE(0.0),
|
.CLKOUT4_PHASE(0.0),
|
.CLKOUT5_PHASE(180.0),
|
.CLKOUT5_PHASE(0.0),
|
.DIVCLK_DIVIDE(1), // Master division value , (1-56)
|
.DIVCLK_DIVIDE(1), // Master division value , (1-56)
|
.REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999)
|
.REF_JITTER1(0.0), // Ref. input jitter in UI (0.000-0.999)
|
.STARTUP_WAIT("FALSE") // Delayu DONE until PLL Locks, ("TRUE"/"FALSE")
|
.STARTUP_WAIT("TRUE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
|
) genclock(
|
) genclock(
|
// Clock outputs: 1-bit (each) output
|
// Clock outputs: 1-bit (each) output
|
.CLKOUT0(i_clk),
|
.CLKOUT0(i_clk),
|
.CLKOUT1(clk_for_ddr),
|
.CLKOUT1(clk_for_ddr),
|
.CLKOUT2(clk2_unused), // Reserved for flash, should we need it
|
.CLKOUT2(mem_serial_clk),
|
.CLKOUT3(enet_clk),
|
.CLKOUT3(mem_serial_clk_inv),
|
.CLKOUT4(clk_analyzer),
|
.CLKOUT4(clk_unused),
|
.CLKOUT5(clk_analyzer_b),
|
.CLKOUT5(enet_clk),
|
.CLKFBOUT(clk_feedback), // 1-bit output, feedback clock
|
.CLKFBOUT(clk_feedback), // 1-bit output, feedback clock
|
.LOCKED(clk_locked),
|
.LOCKED(clk_locked),
|
.CLKIN1(i_clk_100mhz),
|
.CLKIN1(i_clk_100mhz),
|
.PWRDWN(1'b0),
|
.PWRDWN(1'b0),
|
.RST(1'b0),
|
.RST(1'b0),
|
| Line 184... |
Line 185... |
|
|
wire [7:0] rx_data, tx_data;
|
wire [7:0] rx_data, tx_data;
|
wire rx_break, rx_parity_err, rx_frame_err, rx_stb;
|
wire rx_break, rx_parity_err, rx_frame_err, rx_stb;
|
wire tx_stb, tx_busy;
|
wire tx_stb, tx_busy;
|
|
|
|
//
|
|
// RESET LOGIC
|
|
//
|
|
// Okay, so this looks bad at a first read--but it's not really that
|
|
// bad. If you look close, there are two parts to the reset logic.
|
|
// The first is the "PRE"-reset. This is a wire, set from the external
|
|
// reset button. In good old-fashioned asynch-logic to synchronous
|
|
// logic fashion, we synchronize this wire by registering it first
|
|
// to pre_reset, and then to pwr_reset (the actual reset wire).
|
|
//
|
reg pwr_reset, pre_reset;
|
reg pwr_reset, pre_reset;
|
initial pwr_reset = 1'b1;
|
//
|
|
// Logic description starts with the PRE-reset, so as to make certain
|
|
// we include the reset button
|
initial pre_reset = 1'b0;
|
initial pre_reset = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
pre_reset <= ~i_reset_btn;
|
pre_reset <= ~i_reset_btn;
|
|
//
|
|
// and then continues with the actual reset, now that we've
|
|
// synchronized our reset button wire.
|
|
initial pwr_reset = 1'b1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
pwr_reset <= pre_reset;
|
pwr_reset <= pre_reset;
|
|
|
wire w_ck_uart, w_uart_tx;
|
wire w_ck_uart, w_uart_tx;
|
rxuart rcv(i_clk, pwr_reset, bus_uart_setup, i_uart_rx,
|
rxuart rcv(i_clk, pwr_reset, bus_uart_setup, i_uart_rx,
|
| Line 202... |
Line 219... |
tx_stb, tx_data, o_uart_tx, tx_busy);
|
tx_stb, tx_data, o_uart_tx, tx_busy);
|
|
|
|
|
|
|
|
|
|
`ifdef SDRAM_ACCESS
|
|
///
|
|
///
|
|
/// The following lines are included from ddr3insert.v.
|
|
///
|
|
wire w_ddr_reset_n, w_ddr_cke, w_ddr_bus_oe;
|
|
wire [26:0] w_ddr_cmd_a, w_ddr_cmd_b;
|
|
wire [63:0] wi_ddr_data, wo_ddr_data;
|
|
wire [127:0] wide_ddr_data;
|
|
|
|
//
|
|
//
|
|
// Wires for setting up the DDR3 memory
|
|
//
|
|
//
|
|
|
|
// First, let's set up the clock(s)
|
|
xoddrserdesb ddrclk(mem_serial_clk, i_clk, pwr_reset, 8'h66,
|
|
o_ddr_ck_p, o_ddr_ck_n);
|
|
|
|
wire [7:0] w_udqs_in, w_ldqs_in;
|
|
|
|
xioddrserdesb ddrudqs(mem_serial_clk, mem_serial_clk_inv, i_clk,
|
|
~w_ddr_reset_n, w_ddr_cmd_a[0],
|
|
(w_ddr_cmd_b[0])? 8'h66 : 8'h06,
|
|
w_udqs_in,
|
|
io_ddr_dqs_p[1], io_ddr_dqs_n[1]);
|
|
|
|
xioddrserdesb ddrldqs(mem_serial_clk, mem_serial_clk_inv, i_clk,
|
|
~w_ddr_reset_n, w_ddr_cmd_a[0],
|
|
(w_ddr_cmd_b[0])? 8'h66 : 8'h06,
|
|
w_ldqs_in,
|
|
io_ddr_dqs_p[0], io_ddr_dqs_n[0]);
|
|
|
|
// The command wires: CS_N, RAS_N, CAS_N, and WE_N
|
|
xoddrserdes ddrcsn(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
|
{ w_ddr_cmd_a[26], w_ddr_cmd_a[26],
|
|
w_ddr_cmd_a[26], w_ddr_cmd_a[26],
|
|
w_ddr_cmd_b[26], w_ddr_cmd_b[26],
|
|
w_ddr_cmd_b[26], w_ddr_cmd_b[26] }, o_ddr_cs_n);
|
|
|
|
xoddrserdes ddrrasn(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
|
{ w_ddr_cmd_a[25], w_ddr_cmd_a[25],
|
|
w_ddr_cmd_a[25], w_ddr_cmd_a[25],
|
|
w_ddr_cmd_b[25], w_ddr_cmd_b[25],
|
|
w_ddr_cmd_b[25], w_ddr_cmd_b[25] }, o_ddr_ras_n);
|
|
|
|
xoddrserdes ddrcasn(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
|
{ w_ddr_cmd_a[24], w_ddr_cmd_a[24],
|
|
w_ddr_cmd_a[24], w_ddr_cmd_a[24],
|
|
w_ddr_cmd_b[24], w_ddr_cmd_b[24],
|
|
w_ddr_cmd_b[24], w_ddr_cmd_b[24] }, o_ddr_cas_n);
|
|
|
|
xoddrserdes ddrwen(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
|
{ w_ddr_cmd_a[23], w_ddr_cmd_a[23],
|
|
w_ddr_cmd_a[23], w_ddr_cmd_a[23],
|
|
w_ddr_cmd_b[23], w_ddr_cmd_b[23],
|
|
w_ddr_cmd_b[23], w_ddr_cmd_b[23] }, o_ddr_we_n);
|
|
|
|
// Data mask wires, first the upper byte
|
|
xoddrserdes ddrudm(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
|
{ w_ddr_cmd_a[4], w_ddr_cmd_a[4],
|
|
w_ddr_cmd_a[2], w_ddr_cmd_a[2],
|
|
w_ddr_cmd_b[4], w_ddr_cmd_b[4],
|
|
w_ddr_cmd_b[2], w_ddr_cmd_b[2] }, o_ddr_dm[1]);
|
|
// then the lower byte
|
|
xoddrserdes ddrldm(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
|
{ w_ddr_cmd_a[3], w_ddr_cmd_a[3],
|
|
w_ddr_cmd_a[1], w_ddr_cmd_a[1],
|
|
w_ddr_cmd_b[3], w_ddr_cmd_b[3],
|
|
w_ddr_cmd_b[1], w_ddr_cmd_b[1] }, o_ddr_dm[0]);
|
|
|
|
// and the On-Die termination wire
|
|
xoddrserdes ddrodt(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
|
{ w_ddr_cmd_a[0], w_ddr_cmd_a[0],
|
|
w_ddr_cmd_a[0], w_ddr_cmd_a[0],
|
|
w_ddr_cmd_b[0], w_ddr_cmd_b[0],
|
|
w_ddr_cmd_b[0], w_ddr_cmd_b[0] }, o_ddr_odt);
|
|
|
|
//
|
|
// Now for the data, bank, and address wires
|
|
//
|
|
genvar k;
|
|
generate begin
|
|
//
|
|
for(k=0; k<16; k=k+1)
|
|
xioddrserdes ddrdata(mem_serial_clk, mem_serial_clk_inv, i_clk, ~w_ddr_reset_n,
|
|
w_ddr_bus_oe,
|
|
{ wo_ddr_data[48+k], wo_ddr_data[48+k],
|
|
wo_ddr_data[32+k], wo_ddr_data[32+k],
|
|
wo_ddr_data[16+k], wo_ddr_data[16+k],
|
|
wo_ddr_data[ k], wo_ddr_data[ k] },
|
|
{ wide_ddr_data[112+k], wide_ddr_data[96+k],
|
|
wide_ddr_data[ 80+k], wide_ddr_data[64+k],
|
|
wide_ddr_data[ 48+k], wide_ddr_data[32+k],
|
|
wide_ddr_data[ 16+k], wide_ddr_data[ k] },
|
|
io_ddr_data[k]);
|
|
//
|
|
for(k=0; k<3; k=k+1)
|
|
xoddrserdes ddrbank(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
|
{ w_ddr_cmd_a[20+k], w_ddr_cmd_a[20+k],
|
|
w_ddr_cmd_a[20+k], w_ddr_cmd_a[20+k],
|
|
w_ddr_cmd_b[20+k], w_ddr_cmd_b[20+k],
|
|
w_ddr_cmd_b[20+k], w_ddr_cmd_b[20+k] },
|
|
o_ddr_ba[k]);
|
|
//
|
|
for(k=0; k<14; k=k+1)
|
|
xoddrserdes ddraddr(mem_serial_clk, i_clk, ~w_ddr_reset_n,
|
|
{ w_ddr_cmd_a[ 6+k], w_ddr_cmd_a[ 6+k],
|
|
w_ddr_cmd_a[ 6+k], w_ddr_cmd_a[ 6+k],
|
|
w_ddr_cmd_b[ 6+k], w_ddr_cmd_b[ 6+k],
|
|
w_ddr_cmd_b[ 6+k], w_ddr_cmd_b[ 6+k] },
|
|
o_ddr_addr[k]);
|
|
//
|
|
|
|
for(k=0; k<64; k=k+1)
|
|
assign wi_ddr_data[k] = (w_ddr_bus_oe) ? wide_ddr_data[2*k+1]
|
|
: wide_ddr_data[2*k];
|
|
end endgenerate
|
|
|
|
assign o_ddr_reset_n = w_ddr_reset_n;
|
|
assign o_ddr_cke = w_ddr_cke;
|
|
|
|
|
|
///
|
|
///
|
|
///
|
|
///
|
|
`else
|
|
wire w_ddr_reset_n, w_ddr_cke, w_ddr_bus_oe;
|
|
wire [26:0] w_ddr_cmd_a, w_ddr_cmd_b;
|
|
wire [63:0] wi_ddr_data, wo_ddr_data;
|
|
wire [127:0] wide_ddr_data;
|
|
|
|
//
|
|
//
|
|
// Wires for setting up the DDR3 memory
|
|
//
|
|
//
|
|
|
|
// Leave the SDRAM in a permanent state of reset
|
|
assign o_ddr_reset_n = 1'b0;
|
|
// Leave the SDRAM clock ... disabled
|
|
assign o_ddr_cke = 1'b0;
|
|
|
|
// Disable the clock(s)
|
|
OBUFDS(.I(1'b0), .O(o_ddr_ck_p), .OB(o_ddr_ck_n));
|
|
// And the data strobe
|
|
OBUFDS(.I(1'b0), .O(io_ddr_dqs_p[0]), .OB(io_ddr_dqs_n[0]));
|
|
OBUFDS(.I(1'b0), .O(io_ddr_dqs_p[1]), .OB(io_ddr_dqs_n[1]));
|
|
|
|
// Output ... something, anything, on the address lines
|
|
assign o_ddr_cs_n = 1'b1; // Never enable any commands
|
|
assign o_ddr_ras_n = 1'b0;
|
|
assign o_ddr_cas_n = 1'b0;
|
|
assign o_ddr_we_n = 1'b0;
|
|
assign o_ddr_ba = 3'h0;
|
|
assign o_ddr_addr = 14'h0;
|
|
assign o_ddr_dm = 2'b00;
|
|
assign o_ddr_odt = 1'b0;
|
|
|
|
assign io_ddr_data = 16'bzzzz_zzzz_zzzz_zzzz;
|
|
assign wi_ddr_data = io_ddr_data;
|
|
|
|
`endif
|
|
|
|
|
//////
|
//////
|
//
|
//
|
//
|
//
|
| Line 218... |
Line 400... |
wire [1:0] qspi_bmod;
|
wire [1:0] qspi_bmod;
|
wire [3:0] qspi_dat;
|
wire [3:0] qspi_dat;
|
wire [3:0] i_qspi_dat;
|
wire [3:0] i_qspi_dat;
|
|
|
//
|
//
|
wire [31:0] wo_ddr_data, wi_ddr_data;
|
|
wire w_ddr_dqs, w_ddr_dm, w_ddr_bus_oe, w_ddr_odt;
|
|
wire [2:0] w_ddr_ba;
|
|
wire w_ddr_cs_n, w_ddr_ras_n, w_ddr_cas_n, w_ddr_we_n;
|
|
wire [13:0] w_ddr_addr;
|
|
reg [31:0] r_ddr_data;
|
|
|
|
//
|
|
wire w_mdio, w_mdwe;
|
wire w_mdio, w_mdwe;
|
//
|
//
|
wire w_sd_cmd;
|
wire w_sd_cmd;
|
wire [3:0] w_sd_data;
|
wire [3:0] w_sd_data;
|
fastmaster wbbus(i_clk, pwr_reset,
|
fastmaster wbbus(i_clk, pwr_reset,
|
| Line 241... |
Line 415... |
// Board level PMod I/O
|
// Board level PMod I/O
|
i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
|
i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
|
// Quad SPI flash
|
// Quad SPI flash
|
w_qspi_cs_n, w_qspi_sck, qspi_dat, i_qspi_dat, qspi_bmod,
|
w_qspi_cs_n, w_qspi_sck, qspi_dat, i_qspi_dat, qspi_bmod,
|
// DDR3 SDRAM
|
// DDR3 SDRAM
|
o_ddr_reset_n, o_ddr_cke,
|
w_ddr_reset_n, w_ddr_cke, w_ddr_bus_oe,
|
w_ddr_cs_n, w_ddr_ras_n, w_ddr_cas_n, w_ddr_we_n,
|
w_ddr_cmd_a, w_ddr_cmd_b, wo_ddr_data, wi_ddr_data,
|
w_ddr_dqs, w_ddr_dm, w_ddr_odt, w_ddr_bus_oe,
|
|
w_ddr_addr, w_ddr_ba, wo_ddr_data, r_ddr_data,
|
|
// SD Card
|
// SD Card
|
o_sd_sck, w_sd_cmd, w_sd_data, io_sd_cmd, io_sd, i_sd_cs,
|
o_sd_sck, w_sd_cmd, w_sd_data, io_sd_cmd, io_sd, i_sd_cs,
|
// Ethernet control (MDIO) lines
|
// Ethernet control (MDIO) lines
|
o_eth_mdclk, w_mdio, w_mdwe, io_eth_mdio,
|
o_eth_mdclk, w_mdio, w_mdwe, io_eth_mdio,
|
// OLEDRGB PMod wires
|
// OLEDRGB PMod wires
|
| Line 328... |
Line 500... |
//
|
//
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//
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//
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// Wires for setting up the DDR3 memory
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// Wires for setting up the DDR3 memory
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//
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//
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//
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//
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`ifdef SDRAM_ACCESS
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reg [15:0] bottom_half_data;
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always @(posedge i_clk)
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bottom_half_data <= wo_ddr_data[15:0];
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xioddr p0(i_clk, w_ddr_bus_oe, { wo_ddr_data[16], wo_ddr_data[0] },
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{ wi_ddr_data[16], wi_ddr_data[0] }, io_ddr_data[0]);
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xioddr p1(i_clk, w_ddr_bus_oe, { wo_ddr_data[17], wo_ddr_data[1] },
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{ wi_ddr_data[17], wi_ddr_data[1] }, io_ddr_data[1]);
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xioddr p2(i_clk, w_ddr_bus_oe, { wo_ddr_data[18], wo_ddr_data[2] },
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{ wi_ddr_data[18], wi_ddr_data[2] }, io_ddr_data[2]);
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xioddr p3(i_clk, w_ddr_bus_oe, { wo_ddr_data[19], wo_ddr_data[3] },
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{ wi_ddr_data[19], wi_ddr_data[3] }, io_ddr_data[3]);
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xioddr p4(i_clk, w_ddr_bus_oe, { wo_ddr_data[20], wo_ddr_data[4] },
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{ wi_ddr_data[20], wi_ddr_data[4] }, io_ddr_data[4]);
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xioddr p5(i_clk, w_ddr_bus_oe, { wo_ddr_data[21], wo_ddr_data[5] },
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{ wi_ddr_data[21], wi_ddr_data[5] }, io_ddr_data[5]);
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xioddr p6(i_clk, w_ddr_bus_oe, { wo_ddr_data[22], wo_ddr_data[6] },
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{ wi_ddr_data[22], wi_ddr_data[6] }, io_ddr_data[6]);
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xioddr p7(i_clk, w_ddr_bus_oe, { wo_ddr_data[23], wo_ddr_data[7] },
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{ wi_ddr_data[23], wi_ddr_data[7] }, io_ddr_data[7]);
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xioddr p8(i_clk, w_ddr_bus_oe, { wo_ddr_data[24], wo_ddr_data[8] },
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{ wi_ddr_data[24], wi_ddr_data[8] }, io_ddr_data[8]);
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xioddr p9(i_clk, w_ddr_bus_oe, { wo_ddr_data[25], wo_ddr_data[9] },
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{ wi_ddr_data[25], wi_ddr_data[9] }, io_ddr_data[9]);
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xioddr pa(i_clk, w_ddr_bus_oe, { wo_ddr_data[26], wo_ddr_data[10] },
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{ wi_ddr_data[26], wi_ddr_data[10] }, io_ddr_data[10]);
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xioddr pb(i_clk, w_ddr_bus_oe, { wo_ddr_data[27], wo_ddr_data[11] },
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{ wi_ddr_data[27], wi_ddr_data[11] }, io_ddr_data[11]);
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xioddr pc(i_clk, w_ddr_bus_oe, { wo_ddr_data[28], wo_ddr_data[12] },
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{ wi_ddr_data[28], wi_ddr_data[12] }, io_ddr_data[12]);
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xioddr pd(i_clk, w_ddr_bus_oe, { wo_ddr_data[29], wo_ddr_data[13] },
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{ wi_ddr_data[29], wi_ddr_data[13] }, io_ddr_data[13]);
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xioddr pe(i_clk, w_ddr_bus_oe, { wo_ddr_data[30], wo_ddr_data[14] },
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{ wi_ddr_data[30], wi_ddr_data[14] }, io_ddr_data[14]);
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xioddr pf(i_clk, w_ddr_bus_oe, { wo_ddr_data[31], wo_ddr_data[15] },
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{ wi_ddr_data[31], wi_ddr_data[15] }, io_ddr_data[15]);
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always @(posedge i_clk)
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r_ddr_data <= wi_ddr_data;
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wire [7:0] w_dqs_ignore;
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/*
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xioddrds dqs0(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
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wire w_clk_for_ddr;
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{ w_dqs_ignore[0], w_dqs_ignore[1] },
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ODDR #(.DDR_CLK_EDGE("SAME_EDGE"))
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io_ddr_dqs_p[0], io_ddr_dqs_n[0]);
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memclkddr(.Q(w_clk_for_ddr), .C(clk_for_ddr), .CE(1'b1),
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xioddrds dqs1(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
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.D1(1'b0), .D2(1'b1), .R(1'b0), .S(1'b0));
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{ w_dqs_ignore[2], w_dqs_ignore[3] },
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OBUFDS #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
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io_ddr_dqs_p[1], io_ddr_dqs_n[1]);
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clkbuf(.O(o_ddr_ck_p), .OB(o_ddr_ck_n), .I(w_clk_for_ddr));
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*/
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xoddr xcs_n( i_clk, { w_ddr_cs_n, w_ddr_cs_n }, o_ddr_cs_n);
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xoddr xras_n(i_clk, { w_ddr_ras_n, w_ddr_ras_n }, o_ddr_ras_n);
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xoddr xcas_n(i_clk, { w_ddr_cas_n, w_ddr_cas_n }, o_ddr_cas_n);
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xoddr xwe_n( i_clk, { w_ddr_we_n, w_ddr_we_n }, o_ddr_we_n);
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xoddr xba0( i_clk, { w_ddr_ba[0], w_ddr_ba[0] }, o_ddr_ba[0]);
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xoddr xba1( i_clk, { w_ddr_ba[1], w_ddr_ba[1] }, o_ddr_ba[1]);
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xoddr xba2( i_clk, { w_ddr_ba[2], w_ddr_ba[2] }, o_ddr_ba[2]);
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xoddr xaddr0(i_clk, { w_ddr_addr[0], w_ddr_addr[0] }, o_ddr_addr[0]);
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xoddr xaddr1(i_clk, { w_ddr_addr[1], w_ddr_addr[1] }, o_ddr_addr[1]);
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xoddr xaddr2(i_clk, { w_ddr_addr[2], w_ddr_addr[2] }, o_ddr_addr[2]);
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xoddr xaddr3(i_clk, { w_ddr_addr[3], w_ddr_addr[3] }, o_ddr_addr[3]);
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xoddr xaddr4(i_clk, { w_ddr_addr[4], w_ddr_addr[4] }, o_ddr_addr[4]);
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xoddr xaddr5(i_clk, { w_ddr_addr[5], w_ddr_addr[5] }, o_ddr_addr[5]);
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xoddr xaddr6(i_clk, { w_ddr_addr[6], w_ddr_addr[6] }, o_ddr_addr[6]);
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xoddr xaddr7(i_clk, { w_ddr_addr[7], w_ddr_addr[7] }, o_ddr_addr[7]);
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xoddr xaddr8(i_clk, { w_ddr_addr[8], w_ddr_addr[8] }, o_ddr_addr[8]);
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xoddr xaddr9(i_clk, { w_ddr_addr[9], w_ddr_addr[9] }, o_ddr_addr[9]);
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xoddr xaddr10(i_clk,{ w_ddr_addr[10],w_ddr_addr[10]}, o_ddr_addr[10]);
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xoddr xaddr11(i_clk,{ w_ddr_addr[11],w_ddr_addr[11]}, o_ddr_addr[11]);
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xoddr xaddr12(i_clk,{ w_ddr_addr[12],w_ddr_addr[12]}, o_ddr_addr[12]);
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xoddr xaddr13(i_clk,{ w_ddr_addr[13],w_ddr_addr[13]}, o_ddr_addr[13]);
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wire w_clk_for_ddr;
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ODDR #(.DDR_CLK_EDGE("SAME_EDGE"))
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memclkddr(.Q(w_clk_for_ddr), .C(clk_for_ddr), .CE(1'b1),
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.D1(1'b0), .D2(1'b1), .R(1'b0), .S(1'b0));
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OBUFDS #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
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clkbuf(.O(o_ddr_ck_p), .OB(o_ddr_ck_n), .I(w_clk_for_ddr));
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// assign o_ddr_dm[0] = w_ddr_dm;
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// assign o_ddr_dm[1] = w_ddr_dm;
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xoddr xdm0(i_clk,{ w_ddr_dm, w_ddr_dm }, o_ddr_dm[0]);
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xoddr xdm1(i_clk,{ w_ddr_dm, w_ddr_dm }, o_ddr_dm[1]);
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assign o_ddr_odt = (~o_ddr_reset_n)? 1'bz : w_ddr_odt;
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// xlogicanalyzer ladata(i_clk, io_ddr_data[0], w_ddr_debug[3:0]);
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// xlogicanalyzer ladclk(clk_analyzer, clk_analyzer_b,
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// i_clk, o_ddr_ck_p, w_ddr_debug[7:4]);
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assign w_ddr_debug[7:4] = 4'h0;
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assign w_ddr_debug[3:0] = 4'h0;
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`else
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assign o_ddr_cs_n = w_ddr_cs_n;
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assign o_ddr_ras_n = w_ddr_ras_n;
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assign o_ddr_cas_n = w_ddr_cas_n;
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assign o_ddr_we_n = w_ddr_we_n;
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//
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assign o_ddr_ba = w_ddr_ba;
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assign o_ddr_addr = w_ddr_addr;
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//
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assign o_ddr_dm[1:0] = 2'b00;
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assign o_ddr_odt = 1'b0;
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//
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assign io_ddr_data = 16'bzzzz_zzzz_zzzz_zzzz;
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always @(posedge i_clk)
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r_ddr_data = 16'h0000;
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//wire w_clk_for_ddr;
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//ODDR #(.DDR_CLK_EDGE("SAME_EDGE"))
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//memclkddr(.Q(w_clk_for_ddr), .C(clk_for_ddr), .CE(1'b1),
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//.D1(1'b0), .D2(1'b1), .R(1'b0), .S(1'b0));
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OBUFDS #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
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clkbuf(.O(o_ddr_ck_p), .OB(o_ddr_ck_n), .I(1'b1));
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wire [7:0] w_dqs_ignore;
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xioddrds dqs0(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
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{ w_dqs_ignore[0], w_dqs_ignore[1] },
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io_ddr_dqs_p[0], io_ddr_dqs_n[0]);
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xioddrds dqs1(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
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{ w_dqs_ignore[2], w_dqs_ignore[3] },
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io_ddr_dqs_p[1], io_ddr_dqs_n[1]);
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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