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Line 104... |
//
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//
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module gpsclock(i_clk, i_rst, i_pps, o_pps, o_led,
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module gpsclock(i_clk, i_rst, i_pps, o_pps, o_led,
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i_wb_cyc_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_tracking, o_count, o_step, o_err, o_locked, o_dbg);
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o_tracking, o_count, o_step, o_err, o_locked, o_dbg);
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parameter DEFAULT_STEP = 32'h834d_c736;//2^64/81.25 MHz
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parameter [31:0] DEFAULT_STEP = 32'h834d_c736;//2^64/81.25 MHz
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parameter RW=64, // Needs to be 2ceil(Log_2(i_clk frequency))
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parameter RW=64, // Needs to be 2ceil(Log_2(i_clk frequency))
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DW=32, // The width of our data bus
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DW=32, // The width of our data bus
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ONE_SECOND = 0,
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ONE_SECOND = 0,
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NPW=RW-DW, // Width of non-parameter data
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NPW=RW-DW, // Width of non-parameter data
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HRW=RW/2; // Half of RW
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HRW=RW/2; // Half of RW
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Line 436... |
reg delayed_carry;
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reg delayed_carry;
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initial delayed_carry = 0;
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initial delayed_carry = 0;
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wire [31:0] initial_default_step = DEFAULT_STEP;
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wire [31:0] initial_default_step = DEFAULT_STEP;
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// initial o_step = 64'h002af31dc461; // 100MHz
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// initial o_step = 64'h002af31dc461; // 100MHz
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initial o_step = { 16'h00, (({ initial_default_step[27:0], 20'h00 })
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initial o_step = { 16'h00, (({ DEFAULT_STEP[27:0], 20'h00 })
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>> initial_default_step[31:28])};
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>> DEFAULT_STEP[31:28])};
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(dly_config))
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if ((i_rst)||(dly_config))
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o_step <= pre_step;
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o_step <= pre_step;
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`ifndef DEBUG
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`ifndef DEBUG
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else if ((o_tracking) && (tick))
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else if ((o_tracking) && (tick))
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