URL
https://opencores.org/ocsvn/openarty/openarty/trunk
[/] [openarty/] [trunk/] [rtl/] [lleqspi.v] - Diff between revs 3 and 12
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 3 |
Rev 12 |
| Line 295... |
Line 295... |
o_dat <= 4'hd;
|
o_dat <= 4'hd;
|
end
|
end
|
*/
|
*/
|
end
|
end
|
|
|
|
`define EXTRA_DELAY
|
|
`ifdef EXTRA_DELAY
|
|
reg rd_input_2, rd_valid_2, r_spd_2;
|
|
always @(posedge i_clk)
|
|
rd_input_2 <= rd_input;
|
|
always @(posedge i_clk)
|
|
rd_valid_2 <= rd_valid;
|
|
always @(posedge i_clk)
|
|
r_spd_2 <= r_spd;
|
|
`else
|
|
wire rd_input_2, rd_valid_2, r_spd_2;
|
|
assign rd_input_2 = rd_input;
|
|
assign rd_valid_2 = rd_valid;
|
|
assign r_spd_2 = rd_spd;
|
|
`endif
|
|
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
if ((state == `EQSPI_IDLE)||(rd_valid))
|
if ((state == `EQSPI_IDLE)||(rd_valid_2))
|
r_input <= 31'h00;
|
r_input <= 31'h00;
|
else if ((rd_input)&&(r_spd))
|
else if ((rd_input_2)&&(r_spd_2))
|
r_input <= { r_input[26:0], i_dat };
|
r_input <= { r_input[26:0], i_dat };
|
else if (rd_input)
|
else if (rd_input_2)
|
r_input <= { r_input[29:0], i_miso };
|
r_input <= { r_input[29:0], i_miso };
|
|
|
if ((rd_valid)&&(r_spd))
|
if ((rd_valid)&&(rd_spd))
|
o_word <= { r_input[27:0], i_dat };
|
o_word <= { r_input[27:0], i_dat };
|
else if (rd_valid)
|
else if (rd_valid)
|
o_word <= { r_input[30:0], i_miso };
|
o_word <= { r_input[30:0], i_miso };
|
end
|
end
|
|
|
assign o_valid = rd_valid;
|
assign o_valid = rd_valid_2;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.