| Line 1... |
Line 1... |
////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: rxuart.v
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// Filename: rxuart.v
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//
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//
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// Project: FPGA library
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// Project: wbuart32, a full featured UART with simulator
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//
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//
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// Purpose: Receive and decode inputs from a single UART line.
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// Purpose: Receive and decode inputs from a single UART line.
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//
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//
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//
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//
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// To interface with this module, connect it to your system clock,
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// To interface with this module, connect it to your system clock,
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| Line 17... |
Line 17... |
// There is a synchronous reset line, logic high.
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// There is a synchronous reset line, logic high.
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//
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//
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// Now for the setup register. The register is 32 bits, so that this
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// Now for the setup register. The register is 32 bits, so that this
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// UART may be set up over a 32-bit bus.
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// UART may be set up over a 32-bit bus.
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//
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//
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// i_setup[30] True if we are not using hardware flow control. This bit
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// is ignored within this module, as any receive hardware flow
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// control will need to be implemented elsewhere.
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//
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// i_setup[29:28] Indicates the number of data bits per word. This will
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// i_setup[29:28] Indicates the number of data bits per word. This will
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// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
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// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
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// for a six bit word, or 2'b11 for a five bit word.
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// for a six bit word, or 2'b11 for a five bit word.
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//
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//
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// i_setup[27] Indicates whether or not to use one or two stop bits.
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// i_setup[27] Indicates whether or not to use one or two stop bits.
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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Line 92... |
// States: (@ baud counter == 0)
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// States: (@ baud counter == 0)
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// 0 First bit arrives
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// 0 First bit arrives
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// ..7 Bits arrive
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// ..7 Bits arrive
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// 8 Stop bit (x1)
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// 8 Stop bit (x1)
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// 9 Stop bit (x2)
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// 9 Stop bit (x2)
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/// c break condition
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// c break condition
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// d Waiting for the channel to go high
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// d Waiting for the channel to go high
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// e Waiting for the reset to complete
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// e Waiting for the reset to complete
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// f Idle state
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// f Idle state
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`define RXU_BIT_ZERO 4'h0
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`define RXU_BIT_ZERO 4'h0
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`define RXU_BIT_ONE 4'h1
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`define RXU_BIT_ONE 4'h1
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// Unused 4'hc
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// Unused 4'hc
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`define RXU_BREAK 4'hd
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`define RXU_BREAK 4'hd
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`define RXU_RESET_IDLE 4'he
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`define RXU_RESET_IDLE 4'he
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`define RXU_IDLE 4'hf
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`define RXU_IDLE 4'hf
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module rxuart(i_clk, i_reset, i_setup, i_uart, o_wr, o_data, o_break,
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module rxuart(i_clk, i_reset, i_setup, i_uart_rx, o_wr, o_data, o_break,
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o_parity_err, o_frame_err, o_ck_uart);
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o_parity_err, o_frame_err, o_ck_uart);
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// parameter // CLOCKS_PER_BAUD = 25'd004340,
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parameter [30:0] INITIAL_SETUP = 31'd868;
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// BREAK_CONDITION = CLOCKS_PER_BAUD * 12,
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// CLOCKS_PER_HALF_BAUD = CLOCKS_PER_BAUD/2;
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// 8 data bits, no parity, (at least 1) stop bit
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// 8 data bits, no parity, (at least 1) stop bit
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input i_clk, i_reset;
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input i_clk, i_reset;
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input [29:0] i_setup;
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input [30:0] i_setup;
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input i_uart;
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input i_uart_rx;
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output reg o_wr;
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output reg o_wr;
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output reg [7:0] o_data;
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output reg [7:0] o_data;
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output reg o_break;
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output reg o_break;
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output reg o_parity_err, o_frame_err;
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output reg o_parity_err, o_frame_err;
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output wire o_ck_uart;
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output wire o_ck_uart;
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Line 131... |
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wire [27:0] clocks_per_baud, break_condition, half_baud;
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wire [27:0] clocks_per_baud, break_condition, half_baud;
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wire [1:0] data_bits;
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wire [1:0] data_bits;
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wire use_parity, parity_even, dblstop, fixd_parity;
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wire use_parity, parity_even, dblstop, fixd_parity;
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reg [29:0] r_setup;
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reg [29:0] r_setup;
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reg [3:0] state;
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assign clocks_per_baud = { 4'h0, r_setup[23:0] };
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assign clocks_per_baud = { 4'h0, r_setup[23:0] };
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// assign hw_flow_control = !r_setup[30];
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assign data_bits = r_setup[29:28];
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assign data_bits = r_setup[29:28];
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assign dblstop = r_setup[27];
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assign dblstop = r_setup[27];
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assign use_parity = r_setup[26];
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assign use_parity = r_setup[26];
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assign fixd_parity = r_setup[25];
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assign fixd_parity = r_setup[25];
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assign parity_even = r_setup[24];
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assign parity_even = r_setup[24];
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assign break_condition = { r_setup[23:0], 4'h0 };
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assign break_condition = { r_setup[23:0], 4'h0 };
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assign half_baud = { 5'h00, r_setup[23:1] };
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assign half_baud = { 5'h00, r_setup[23:1] }-28'h1;
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reg [27:0] baud_counter;
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reg zero_baud_counter;
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// Since this is an asynchronous receiver, we need to register our
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// input a couple of clocks over to avoid any problems with
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// metastability. We do that here, and then ignore all but the
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// ck_uart wire.
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reg q_uart, qq_uart, ck_uart;
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reg q_uart, qq_uart, ck_uart;
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initial q_uart = 1'b0;
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initial q_uart = 1'b0;
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initial qq_uart = 1'b0;
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initial qq_uart = 1'b0;
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initial ck_uart = 1'b0;
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initial ck_uart = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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q_uart <= i_uart;
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q_uart <= i_uart_rx;
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qq_uart <= q_uart;
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qq_uart <= q_uart;
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ck_uart <= qq_uart;
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ck_uart <= qq_uart;
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end
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end
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// In case anyone else wants this clocked, stabilized value, we
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// offer it on our output.
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assign o_ck_uart = ck_uart;
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assign o_ck_uart = ck_uart;
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// Keep track of the number of clocks since the last change.
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//
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// This is used to determine if we are in either a break or an idle
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// condition, as discussed further below.
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reg [27:0] chg_counter;
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reg [27:0] chg_counter;
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initial chg_counter = 28'h00;
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initial chg_counter = 28'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_reset)
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if (i_reset)
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chg_counter <= 28'h00;
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chg_counter <= 28'h00;
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else if (qq_uart != ck_uart)
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else if (qq_uart != ck_uart)
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chg_counter <= 28'h00;
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chg_counter <= 28'h00;
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else if (chg_counter < break_condition)
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else if (chg_counter < break_condition)
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chg_counter <= chg_counter + 1;
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chg_counter <= chg_counter + 1;
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reg line_synch;
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// Are we in a break condition?
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initial line_synch = 1'b0;
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//
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// A break condition exists if the line is held low for longer than
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// a data word. Hence, we keep track of when the last change occurred.
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// If it was more than break_condition clocks ago, and the current input
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// value is a 0, then we're in a break--and nothing can be read until
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// the line idles again.
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initial o_break = 1'b0;
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initial o_break = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_break <= ((chg_counter >= break_condition)&&(~ck_uart))? 1'b1:1'b0;
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o_break <= ((chg_counter >= break_condition)&&(~ck_uart))? 1'b1:1'b0;
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// Are we between characters?
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//
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// The opposite of a break condition is where the line is held high
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// for more clocks than would be in a character. When this happens,
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// we know we have synchronization--otherwise, we might be sampling
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// from within a data word.
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//
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// This logic is used later to hold the RXUART in a reset condition
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// until we know we are between data words. At that point, we should
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// be able to hold on to our synchronization.
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reg line_synch;
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initial line_synch = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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line_synch <= ((chg_counter >= break_condition)&&(ck_uart));
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line_synch <= ((chg_counter >= break_condition)&&(ck_uart));
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reg [3:0] state;
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// Are we in the middle of a baud iterval? Specifically, are we
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reg [27:0] baud_counter;
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// in the middle of a start bit? Set this to high if so. We'll use
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reg [7:0] data_reg;
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// this within our state machine to transition out of the IDLE
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reg calc_parity, zero_baud_counter, half_baud_time;
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// state.
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initial o_wr = 1'b0;
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reg half_baud_time;
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initial half_baud_time = 0;
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always @(posedge i_clk)
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half_baud_time <= (~ck_uart)&&(chg_counter >= half_baud);
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// Allow our controlling processor to change our setup at any time
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// outside of receiving/processing a character.
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initial r_setup = INITIAL_SETUP[29:0];
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always @(posedge i_clk)
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if (state >= `RXU_RESET_IDLE)
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r_setup <= i_setup[29:0];
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// Our monster state machine. YIKES!
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//
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// Yeah, this may be more complicated than it needs to be. The basic
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// progression is:
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// RESET -> RESET_IDLE -> (when line is idle) -> IDLE
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// IDLE -> bit 0 -> bit 1 -> bit_{ndatabits} ->
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// (optional) PARITY -> STOP -> (optional) SECOND_STOP
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// -> IDLE
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// ANY -> (on break) BREAK -> IDLE
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//
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// There are 16 states, although all are not used. These are listed
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// at the top of this file.
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//
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// Logic inputs (12): (I've tried to minimize this number)
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// state (4)
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// i_reset
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// line_synch
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// o_break
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// ckuart
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// half_baud_time
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// zero_baud_counter
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// use_parity
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// dblstop
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// Logic outputs (4):
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// state
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//
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initial state = `RXU_RESET_IDLE;
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initial state = `RXU_RESET_IDLE;
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initial o_parity_err = 1'b0;
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initial o_frame_err = 1'b0;
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// initial baud_counter = clocks_per_baud;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if (i_reset)
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if (i_reset)
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begin
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o_wr <= 1'b0;
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o_data <= 8'h00;
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state <= `RXU_RESET_IDLE;
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state <= `RXU_RESET_IDLE;
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baud_counter <= clocks_per_baud-28'h01;// Set, not reset
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else if (state == `RXU_RESET_IDLE)
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data_reg <= 8'h00;
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calc_parity <= 1'b0;
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o_parity_err <= 1'b0;
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o_frame_err <= 1'b0;
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end else if (state == `RXU_RESET_IDLE)
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begin
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begin
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r_setup <= i_setup;
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data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
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baud_counter <= clocks_per_baud-28'h01;// Set, not reset
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if (line_synch)
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if (line_synch)
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// Goto idle state from a reset
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// Goto idle state from a reset
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state <= `RXU_IDLE;
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state <= `RXU_IDLE;
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else // Otherwise, stay in this condition 'til reset
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else // Otherwise, stay in this condition 'til reset
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state <= `RXU_RESET_IDLE;
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state <= `RXU_RESET_IDLE;
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calc_parity <= 1'b0;
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o_parity_err <= 1'b0;
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o_frame_err <= 1'b0;
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end else if (o_break)
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end else if (o_break)
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begin // We are in a break condition
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begin // We are in a break condition
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state <= `RXU_BREAK;
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state <= `RXU_BREAK;
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o_wr <= 1'b0;
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o_data <= 8'h00;
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baud_counter <= clocks_per_baud-28'h01;// Set, not reset
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data_reg <= 8'h00;
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calc_parity <= 1'b0;
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o_parity_err <= 1'b0;
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o_frame_err <= 1'b0;
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r_setup <= i_setup;
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end else if (state == `RXU_BREAK)
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end else if (state == `RXU_BREAK)
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begin // Goto idle state following return ck_uart going high
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begin // Goto idle state following return ck_uart going high
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data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
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baud_counter <= clocks_per_baud - 28'h01;
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if (ck_uart)
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if (ck_uart)
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state <= `RXU_IDLE;
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state <= `RXU_IDLE;
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else
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else
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state <= `RXU_BREAK;
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state <= `RXU_BREAK;
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calc_parity <= 1'b0;
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o_parity_err <= 1'b0;
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o_frame_err <= 1'b0;
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r_setup <= i_setup;
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end else if (state == `RXU_IDLE)
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end else if (state == `RXU_IDLE)
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begin // Idle state, independent of baud counter
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begin // Idle state, independent of baud counter
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r_setup <= i_setup;
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data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0;
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baud_counter <= clocks_per_baud - 28'h01;
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if ((~ck_uart)&&(half_baud_time))
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if ((~ck_uart)&&(half_baud_time))
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begin
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begin
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// We are in the center of a valid start bit
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// We are in the center of a valid start bit
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case (data_bits)
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case (data_bits)
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2'b00: state <= `RXU_BIT_ZERO;
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2'b00: state <= `RXU_BIT_ZERO;
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| Line 241... |
Line 283... |
2'b10: state <= `RXU_BIT_TWO;
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2'b10: state <= `RXU_BIT_TWO;
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2'b11: state <= `RXU_BIT_THREE;
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2'b11: state <= `RXU_BIT_THREE;
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endcase
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endcase
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end else // Otherwise, just stay here in idle
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end else // Otherwise, just stay here in idle
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state <= `RXU_IDLE;
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state <= `RXU_IDLE;
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calc_parity <= 1'b0;
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o_parity_err <= 1'b0;
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o_frame_err <= 1'b0;
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end else if (zero_baud_counter)
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end else if (zero_baud_counter)
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begin
|
begin
|
baud_counter <= clocks_per_baud-28'h1;
|
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if (state < `RXU_BIT_SEVEN)
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if (state < `RXU_BIT_SEVEN)
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begin
|
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// Data arrives least significant bit first.
|
// Data arrives least significant bit first.
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// By the time this is clocked in, it's what
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// By the time this is clocked in, it's what
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// you'll have.
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// you'll have.
|
data_reg <= { ck_uart, data_reg[7:1] };
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calc_parity <= calc_parity ^ ck_uart;
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o_data <= 8'h00;
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o_wr <= 1'b0;
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state <= state + 1;
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state <= state + 1;
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o_parity_err <= 1'b0;
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else if (state == `RXU_BIT_SEVEN)
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o_frame_err <= 1'b0;
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end else if (state == `RXU_BIT_SEVEN)
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begin
|
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data_reg <= { ck_uart, data_reg[7:1] };
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calc_parity <= calc_parity ^ ck_uart;
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o_data <= 8'h00;
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o_wr <= 1'b0;
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state <= (use_parity) ? `RXU_PARITY:`RXU_STOP;
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state <= (use_parity) ? `RXU_PARITY:`RXU_STOP;
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o_parity_err <= 1'b0;
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else if (state == `RXU_PARITY)
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o_frame_err <= 1'b0;
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end else if (state == `RXU_PARITY)
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begin
|
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if (fixd_parity)
|
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o_parity_err <= (ck_uart ^ parity_even);
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else
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o_parity_err <= ((parity_even && (calc_parity != ck_uart))
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||((~parity_even)&&(calc_parity==ck_uart)));
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state <= `RXU_STOP;
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state <= `RXU_STOP;
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o_frame_err <= 1'b0;
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else if (state == `RXU_STOP)
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end else if (state == `RXU_STOP)
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begin // Stop (or parity) bit(s)
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begin // Stop (or parity) bit(s)
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case (data_bits)
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if (~ck_uart) // On frame error, wait 4 ch idle
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2'b00: o_data <= data_reg;
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2'b01: o_data <= { 1'b0, data_reg[7:1] };
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2'b10: o_data <= { 2'b0, data_reg[7:2] };
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2'b11: o_data <= { 3'b0, data_reg[7:3] };
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endcase
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o_wr <= 1'b1; // Pulse the write
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o_frame_err <= (~ck_uart);
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if (~ck_uart)
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state <= `RXU_RESET_IDLE;
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state <= `RXU_RESET_IDLE;
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else if (dblstop)
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else if (dblstop)
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state <= `RXU_SECOND_STOP;
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state <= `RXU_SECOND_STOP;
|
else
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else
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state <= `RXU_IDLE;
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state <= `RXU_IDLE;
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// o_parity_err <= 1'b0;
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|
end else // state must equal RX_SECOND_STOP
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end else // state must equal RX_SECOND_STOP
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begin
|
begin
|
if (~ck_uart)
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if (~ck_uart) // On frame error, wait 4 ch idle
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begin
|
|
o_frame_err <= 1'b1;
|
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state <= `RXU_RESET_IDLE;
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state <= `RXU_RESET_IDLE;
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end else begin
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else
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state <= `RXU_IDLE;
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state <= `RXU_IDLE;
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o_frame_err <= 1'b0;
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|
end
|
end
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o_parity_err <= 1'b0;
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|
end
|
end
|
end else begin
|
end
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o_wr <= 1'b0; // data_reg = data_reg
|
|
baud_counter <= baud_counter - 28'd1;
|
// Data bit capture logic.
|
|
//
|
|
// This is drastically simplified from the state machine above, based
|
|
// upon: 1) it doesn't matter what it is until the end of a captured
|
|
// byte, and 2) the data register will flush itself of any invalid
|
|
// data in all other cases. Hence, let's keep it real simple.
|
|
// The only trick, though, is that if we have parity, then the data
|
|
// register needs to be held through that state without getting
|
|
// updated.
|
|
reg [7:0] data_reg;
|
|
always @(posedge i_clk)
|
|
if ((zero_baud_counter)&&(state != `RXU_PARITY))
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data_reg <= { ck_uart, data_reg[7:1] };
|
|
|
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// Parity calculation logic
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//
|
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// As with the data capture logic, all that must be known about this
|
|
// bit is that it is the exclusive-OR of all bits prior. The first
|
|
// of those will follow idle, so we set ourselves to zero on idle.
|
|
// Then, as we walk through the states of a bit, all will adjust this
|
|
// value up until the parity bit, where the value will be read. Setting
|
|
// it then or after will be irrelevant, so ... this should be good
|
|
// and simplified. Note--we don't need to adjust this on reset either,
|
|
// since the reset state will lead to the idle state where we'll be
|
|
// reset before any transmission takes place.
|
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reg calc_parity;
|
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always @(posedge i_clk)
|
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if (state == `RXU_IDLE)
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calc_parity <= 0;
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else if (zero_baud_counter)
|
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calc_parity <= calc_parity ^ ck_uart;
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|
|
|
// Parity error logic
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//
|
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// Set during the parity bit interval, read during the last stop bit
|
|
// interval, cleared on BREAK, RESET_IDLE, or IDLE states.
|
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initial o_parity_err = 1'b0;
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|
always @(posedge i_clk)
|
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if ((zero_baud_counter)&&(state == `RXU_PARITY))
|
|
begin
|
|
if (fixd_parity)
|
|
// Fixed parity bit--independent of any dat
|
|
// value.
|
|
o_parity_err <= (ck_uart ^ parity_even);
|
|
else if (parity_even)
|
|
// Parity even: The XOR of all bits including
|
|
// the parity bit must be zero.
|
|
o_parity_err <= (calc_parity != ck_uart);
|
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else
|
|
// Parity odd: the parity bit must equal the
|
|
// XOR of all the data bits.
|
|
o_parity_err <= (calc_parity == ck_uart);
|
|
end else if (state >= `RXU_BREAK)
|
o_parity_err <= 1'b0;
|
o_parity_err <= 1'b0;
|
|
|
|
// Frame error determination
|
|
//
|
|
// For the purpose of this controller, a frame error is defined as a
|
|
// stop bit (or second stop bit, if so enabled) not being high midway
|
|
// through the stop baud interval. The frame error value is
|
|
// immediately read, so we can clear it under all other circumstances.
|
|
// Specifically, we want it clear in RXU_BREAK, RXU_RESET_IDLE, and
|
|
// most importantly in RXU_IDLE.
|
|
initial o_frame_err = 1'b0;
|
|
always @(posedge i_clk)
|
|
if ((zero_baud_counter)&&((state == `RXU_STOP)
|
|
||(state == `RXU_SECOND_STOP)))
|
|
o_frame_err <= (o_frame_err)||(~ck_uart);
|
|
else if ((zero_baud_counter)||(state >= `RXU_BREAK))
|
o_frame_err <= 1'b0;
|
o_frame_err <= 1'b0;
|
end
|
|
end
|
|
|
|
initial zero_baud_counter = 1'b0;
|
// Our data bit logic doesn't need nearly the complexity of all that
|
|
// work above. Indeed, we only need to know if we are at the end of
|
|
// a stop bit, in which case we copy the data_reg into our output
|
|
// data register, o_data.
|
|
//
|
|
// We would also set o_wr to be true when this is the case, but ... we
|
|
// won't know if there is a frame error on the second stop bit for
|
|
// another baud interval yet. So, instead, we set up the logic so that
|
|
// we know on the next zero baud counter that we can write out. That's
|
|
// the purpose of pre_wr.
|
|
initial o_data = 8'h00;
|
|
reg pre_wr;
|
|
initial pre_wr = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
zero_baud_counter <= (baud_counter == 28'h01);
|
if (i_reset)
|
|
begin
|
|
pre_wr <= 1'b0;
|
|
o_data <= 8'h00;
|
|
end else if ((zero_baud_counter)&&(state == `RXU_STOP))
|
|
begin
|
|
pre_wr <= 1'b1;
|
|
case (data_bits)
|
|
2'b00: o_data <= data_reg;
|
|
2'b01: o_data <= { 1'b0, data_reg[7:1] };
|
|
2'b10: o_data <= { 2'b0, data_reg[7:2] };
|
|
2'b11: o_data <= { 3'b0, data_reg[7:3] };
|
|
endcase
|
|
end else if ((zero_baud_counter)||(state == `RXU_IDLE))
|
|
pre_wr <= 1'b0;
|
|
|
initial half_baud_time = 0;
|
// Create an output strobe, true for one clock only, once we know
|
|
// all we need to know. o_data will be set on the last baud interval,
|
|
// o_parity_err on the last parity baud interval (if it existed,
|
|
// cleared otherwise, so ... we should be good to go here.)
|
|
initial o_wr = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
half_baud_time <= (~ck_uart)&&(chg_counter >= half_baud);
|
if ((zero_baud_counter)||(state == `RXU_IDLE))
|
|
o_wr <= (pre_wr)&&(!i_reset);
|
|
else
|
|
o_wr <= 1'b0;
|
|
|
|
// The baud counter
|
|
//
|
|
// This is used as a "clock divider" if you will, but the clock needs
|
|
// to be reset before any byte can be decoded. In all other respects,
|
|
// we set ourselves up for clocks_per_baud counts between baud
|
|
// intervals.
|
|
always @(posedge i_clk)
|
|
if (i_reset)
|
|
baud_counter <= clocks_per_baud-28'h01;
|
|
else if (zero_baud_counter)
|
|
baud_counter <= clocks_per_baud-28'h01;
|
|
else case(state)
|
|
`RXU_RESET_IDLE:baud_counter <= clocks_per_baud-28'h01;
|
|
`RXU_BREAK: baud_counter <= clocks_per_baud-28'h01;
|
|
`RXU_IDLE: baud_counter <= clocks_per_baud-28'h01;
|
|
default: baud_counter <= baud_counter-28'h01;
|
|
endcase
|
|
|
|
// zero_baud_counter
|
|
//
|
|
// Rather than testing whether or not (baud_counter == 0) within our
|
|
// (already too complicated) state transition tables, we use
|
|
// zero_baud_counter to pre-charge that test on the clock
|
|
// before--cleaning up some otherwise difficult timing dependencies.
|
|
initial zero_baud_counter = 1'b0;
|
|
always @(posedge i_clk)
|
|
if (state == `RXU_IDLE)
|
|
zero_baud_counter <= 1'b0;
|
|
else
|
|
zero_baud_counter <= (baud_counter == 28'h01);
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
