| Line 94... |
Line 94... |
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//
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//
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// Some WB simplifications:
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// Some WB simplifications:
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//
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//
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reg r_cmd_busy;
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reg r_cmd_busy;
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wire wb_stb, write_stb, cmd_stb, new_data, new_cmd;
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wire [1:0] wb_addr;
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wire [31:0] wb_data;
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`ifdef WB_CLOCK
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wire wb_stb, write_stb, cmd_stb; // read_stb
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wire wb_stb, write_stb, cmd_stb; // read_stb
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assign wb_stb = ((i_wb_cyc)&&(i_wb_stb)&&(~o_wb_stall));
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assign wb_stb = ((i_wb_stb)&&(~o_wb_stall));
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assign write_stb = ((wb_stb)&&( i_wb_we));
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assign write_stb = ((wb_stb)&&( i_wb_we));
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// assign read_stb = ((wb_stb)&&(~i_wb_we));
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// assign read_stb = ((wb_stb)&&(~i_wb_we));
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assign cmd_stb = (~r_cmd_busy)&&(write_stb)
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assign cmd_stb = (~r_cmd_busy)&&(write_stb)
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&&(i_wb_addr==`SDSPI_CMD_ADDRESS);
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&&(i_wb_addr==`SDSPI_CMD_ADDRESS);
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assign wb_addr = i_wb_addr;
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assign wb_data = i_wb_data;
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assign new_cmd = cmd_stb;
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assign new_data = (i_wb_stb)&&(~o_wb_stall)&&(i_wb_we)
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&&(i_wb_addr == `SDSPI_DAT_ADDRESS);
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`else
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reg r_wb_stb, r_write_stb, r_cmd_stb, r_new_data;
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reg [1:0] r_wb_addr;
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reg [31:0] r_wb_data;
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always @(posedge i_clk)
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r_wb_stb <= ((i_wb_stb)&&(~o_wb_stall));
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always @(posedge i_clk)
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r_write_stb <= ((i_wb_stb)&&(~o_wb_stall)&&(i_wb_we));
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always @(posedge i_clk)
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r_cmd_stb <= (~r_cmd_busy)&&(i_wb_stb)&&(~o_wb_stall)&&(i_wb_we)
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&&(i_wb_addr == `SDSPI_CMD_ADDRESS);
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always @(posedge i_clk)
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r_new_data <= (i_wb_stb)&&(~o_wb_stall)&&(i_wb_we)
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&&(i_wb_addr == `SDSPI_DAT_ADDRESS);
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always @(posedge i_clk)
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r_wb_addr <= i_wb_addr;
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always @(posedge i_clk)
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r_wb_data <= i_wb_data;
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assign wb_stb = r_wb_stb;
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assign write_stb= r_write_stb;
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assign cmd_stb = r_cmd_stb;
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assign new_cmd = r_cmd_stb;
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assign new_data = r_new_data;
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assign wb_addr = r_wb_addr;
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assign wb_data = r_wb_data;
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`endif
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//
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//
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// Access to our lower-level SDSPI driver, the one that actually
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// Access to our lower-level SDSPI driver, the one that actually
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// uses/sets the SPI ports
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// uses/sets the SPI ports
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| Line 181... |
Line 218... |
reg [25:0] r_watchdog;
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reg [25:0] r_watchdog;
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reg r_watchdog_err;
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reg r_watchdog_err;
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reg pre_cmd_state;
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reg pre_cmd_state;
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// Relieve some stress from the WB bus timing
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// Relieve some stress from the WB bus timing
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reg new_data, new_cmd;
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reg [31:0] r_wb_data;
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always @(posedge i_clk)
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new_data <= (write_stb)&&(i_wb_addr == `SDSPI_DAT_ADDRESS);
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always @(posedge i_clk)
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new_cmd <= (~r_cmd_busy)&&(write_stb)
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&&(i_wb_addr==`SDSPI_CMD_ADDRESS);
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always @(posedge i_clk)
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r_wb_data <= i_wb_data;
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initial r_cmd_busy = 1'b0;
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initial r_cmd_busy = 1'b0;
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initial r_data_reg = 32'h00;
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initial r_data_reg = 32'h00;
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initial r_last_r_one = 8'hff;
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initial r_last_r_one = 8'hff;
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initial ll_cmd_stb = 1'b0;
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initial ll_cmd_stb = 1'b0;
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| Line 357... |
Line 384... |
end else if (new_cmd)
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end else if (new_cmd)
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begin // Command write
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begin // Command write
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// Clear the error on any write, whether a commanding
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// Clear the error on any write, whether a commanding
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// one or not. -- provided the user requests clearing
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// one or not. -- provided the user requests clearing
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// it (by setting the bit high)
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// it (by setting the bit high)
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r_cmd_err <= (r_cmd_err)&&(~r_wb_data[15]);
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r_cmd_err <= (r_cmd_err)&&(~wb_data[15]);
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// In a similar fashion, we can switch fifos even if
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// In a similar fashion, we can switch fifos even if
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// not in the middle of a command
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// not in the middle of a command
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r_fifo_id <= r_wb_data[12];
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r_fifo_id <= wb_data[12];
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//
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//
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// Doesn't matter what this is set to as long as we
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// Doesn't matter what this is set to as long as we
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// aren't busy, so we can set it irrelevantly here.
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// aren't busy, so we can set it irrelevantly here.
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ll_cmd_dat <= r_wb_data[7:0];
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ll_cmd_dat <= wb_data[7:0];
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//
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//
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// Note that we only issue a write upon receiving a
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// Note that we only issue a write upon receiving a
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// valid command. Such a command is 8 bits, and must
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// valid command. Such a command is 8 bits, and must
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// start with its high order bits set to zero and one.
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// start with its high order bits set to zero and one.
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// Hence ... we test for that here.
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// Hence ... we test for that here.
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if (r_wb_data[7:6] == 2'b01)
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if (wb_data[7:6] == 2'b01)
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begin // Issue a command
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begin // Issue a command
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//
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//
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r_cmd_busy <= 1'b1;
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r_cmd_busy <= 1'b1;
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//
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//
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ll_cmd_stb <= 1'b1;
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ll_cmd_stb <= 1'b1;
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r_cmd_resp <= r_wb_data[9:8];
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r_cmd_resp <= wb_data[9:8];
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//
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//
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r_cmd_crc_stb <= 1'b1;
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r_cmd_crc_stb <= 1'b1;
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//
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//
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r_fifo_wr <= r_wb_data[10];
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r_fifo_wr <= wb_data[10];
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r_use_fifo <= r_wb_data[11];
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r_use_fifo <= wb_data[11];
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//
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//
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end else if (r_wb_data[7])
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end else if (wb_data[7])
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// If, on the other hand, the command was invalid,
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// If, on the other hand, the command was invalid,
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// then it must have been an attempt to read our
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// then it must have been an attempt to read our
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// internal configuration. So we'll place that on
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// internal configuration. So we'll place that on
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// our data register.
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// our data register.
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r_data_reg <= { 8'h00,
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r_data_reg <= { 8'h00,
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4'h0, max_lgblklen,
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4'h0, max_lgblklen,
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4'h0, r_lgblklen, 1'b0, r_sdspi_clk };
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4'h0, r_lgblklen, 1'b0, r_sdspi_clk };
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end else if (new_data) // Data write
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end else if (new_data) // Data write
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r_data_reg <= r_wb_data;
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r_data_reg <= wb_data;
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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pre_cmd_state <= (ll_cmd_stb)&&(ll_idle);
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pre_cmd_state <= (ll_cmd_stb)&&(ll_idle);
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| Line 477... |
Line 504... |
begin
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begin
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// Update our internal configuration parameters, unconnected
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// Update our internal configuration parameters, unconnected
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// with the card. These include the speed of the interface,
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// with the card. These include the speed of the interface,
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// and the size of the block length to expect as part of a FIFO
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// and the size of the block length to expect as part of a FIFO
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// command.
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// command.
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if ((new_cmd)&&(r_wb_data[7:6]==2'b11)&&(~r_data_reg[7])
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if ((new_cmd)&&(wb_data[7:6]==2'b11)&&(~r_data_reg[7])
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&&(r_data_reg[15:12]==4'h00))
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&&(r_data_reg[15:12]==4'h00))
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begin
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begin
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if (|r_data_reg[6:0])
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if (|r_data_reg[6:0])
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r_sdspi_clk <= r_data_reg[6:0];
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r_sdspi_clk <= r_data_reg[6:0];
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if (|r_data_reg[11:8])
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if (|r_data_reg[11:8])
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| Line 490... |
Line 517... |
r_lgblklen <= max_lgblklen;
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r_lgblklen <= max_lgblklen;
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end
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end
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assign need_reset = 1'b0;
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assign need_reset = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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case(i_wb_addr)
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case(wb_addr)
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`SDSPI_CMD_ADDRESS:
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`SDSPI_CMD_ADDRESS:
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o_wb_data <= { need_reset, 11'h00,
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o_wb_data <= { need_reset, 11'h00,
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3'h0, fifo_crc_err,
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3'h0, fifo_crc_err,
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r_cmd_err, r_cmd_busy, 1'b0, r_fifo_id,
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r_cmd_err, r_cmd_busy, 1'b0, r_fifo_id,
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r_use_fifo, r_fifo_wr, r_cmd_resp,
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r_use_fifo, r_fifo_wr, r_cmd_resp,
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| Line 522... |
Line 549... |
// Let's work with our FIFO memory here ...
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// Let's work with our FIFO memory here ...
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//
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//
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//
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//
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if ((write_stb)&&(i_wb_addr == `SDSPI_CMD_ADDRESS))
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if ((write_stb)&&(wb_addr == `SDSPI_CMD_ADDRESS))
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begin // Command write
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begin // Command write
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// Clear the read/write address
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// Clear the read/write address
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fifo_wb_addr <= {(LGFIFOLN){1'b0}};
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fifo_wb_addr <= {(LGFIFOLN){1'b0}};
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end else if ((wb_stb)&&(i_wb_addr[1]))
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end else if ((wb_stb)&&(wb_addr[1]))
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begin // On read or write, of either FIFO,
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begin // On read or write, of either FIFO,
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// we increase our pointer
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// we increase our pointer
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fifo_wb_addr <= fifo_wb_addr + 1;
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fifo_wb_addr <= fifo_wb_addr + 1;
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// And let ourselves know we need to update ourselves
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// And let ourselves know we need to update ourselves
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// on the next clock
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// on the next clock
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| Line 562... |
Line 589... |
pre_fifo_addr_inc_wr <= ((ll_fifo_wr)&&(ll_out_stb)&&(r_have_start_token));
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pre_fifo_addr_inc_wr <= ((ll_fifo_wr)&&(ll_out_stb)&&(r_have_start_token));
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always @(posedge i_clk)
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always @(posedge i_clk)
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pre_fifo_addr_inc_rd <= ((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle));//&&(ll_fifo_pkt_state[2:0]!=3'b000));
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pre_fifo_addr_inc_rd <= ((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle));//&&(ll_fifo_pkt_state[2:0]!=3'b000));
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always @(posedge i_clk)
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always @(posedge i_clk)
|
begin
|
begin
|
// if ((write_stb)&&(i_wb_addr == `SDSPI_CMD_ADDRESS)&&(i_wb_data[11]))
|
|
// ll_fifo_addr <= {(LGFIFOLN+2){1'b0}};
|
|
if (~r_cmd_busy)
|
if (~r_cmd_busy)
|
ll_fifo_addr <= {(LGFIFOLN+2){1'b0}};
|
ll_fifo_addr <= {(LGFIFOLN+2){1'b0}};
|
else if ((pre_fifo_addr_inc_wr)||(pre_fifo_addr_inc_rd))
|
else if ((pre_fifo_addr_inc_wr)||(pre_fifo_addr_inc_rd))
|
ll_fifo_addr <= ll_fifo_addr + 1;
|
ll_fifo_addr <= ll_fifo_addr + 1;
|
end
|
end
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| Line 602... |
Line 627... |
pre_fifo_a_wr <= (ll_fifo_wr)&&(ll_out_stb)&&(~r_fifo_id)&&(ll_fifo_wr_state == 2'b00);
|
pre_fifo_a_wr <= (ll_fifo_wr)&&(ll_out_stb)&&(~r_fifo_id)&&(ll_fifo_wr_state == 2'b00);
|
pre_fifo_b_wr <= (ll_fifo_wr)&&(ll_out_stb)&&( r_fifo_id)&&(ll_fifo_wr_state == 2'b00);
|
pre_fifo_b_wr <= (ll_fifo_wr)&&(ll_out_stb)&&( r_fifo_id)&&(ll_fifo_wr_state == 2'b00);
|
fifo_wr_crc_stb <= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b00)&&(r_have_start_token);
|
fifo_wr_crc_stb <= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b00)&&(r_have_start_token);
|
pre_fifo_crc_a<= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b01);
|
pre_fifo_crc_a<= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b01);
|
pre_fifo_crc_b<= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b10);
|
pre_fifo_crc_b<= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b10);
|
clear_fifo_crc <= (new_cmd)&&(r_wb_data[15]);
|
clear_fifo_crc <= (new_cmd)&&(wb_data[15]);
|
end
|
end
|
|
|
reg fifo_a_wr, fifo_b_wr;
|
reg fifo_a_wr, fifo_b_wr;
|
reg [3:0] fifo_a_wr_mask, fifo_b_wr_mask;
|
reg [3:0] fifo_a_wr_mask, fifo_b_wr_mask;
|
reg [(LGFIFOLN-1):0] fifo_a_wr_addr, fifo_b_wr_addr;
|
reg [(LGFIFOLN-1):0] fifo_a_wr_addr, fifo_b_wr_addr;
|
| Line 615... |
Line 640... |
initial fifo_crc_err = 1'b0;
|
initial fifo_crc_err = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin // One and only memory write allowed
|
begin // One and only memory write allowed
|
fifo_a_wr <= 1'b0;
|
fifo_a_wr <= 1'b0;
|
fifo_a_wr_data <= { ll_out_dat, ll_out_dat, ll_out_dat, ll_out_dat };
|
fifo_a_wr_data <= { ll_out_dat, ll_out_dat, ll_out_dat, ll_out_dat };
|
if ((write_stb)&&(i_wb_addr[1:0]==2'b10))
|
if ((write_stb)&&(wb_addr[1:0]==2'b10))
|
begin
|
begin
|
fifo_a_wr <= 1'b1;
|
fifo_a_wr <= 1'b1;
|
fifo_a_wr_mask <= 4'b1111;
|
fifo_a_wr_mask <= 4'b1111;
|
fifo_a_wr_addr <= fifo_wb_addr;
|
fifo_a_wr_addr <= fifo_wb_addr;
|
fifo_a_wr_data <= i_wb_data;
|
fifo_a_wr_data <= wb_data;
|
end else if (pre_fifo_a_wr)
|
end else if (pre_fifo_a_wr)
|
begin
|
begin
|
fifo_a_wr <= 1'b1;
|
fifo_a_wr <= 1'b1;
|
fifo_a_wr_addr <= ll_fifo_addr[(LGFIFOLN+1):2];
|
fifo_a_wr_addr <= ll_fifo_addr[(LGFIFOLN+1):2];
|
case(ll_fifo_addr[1:0])
|
case(ll_fifo_addr[1:0])
|
| Line 644... |
Line 669... |
if ((fifo_a_wr)&&(fifo_a_wr_mask[3]))
|
if ((fifo_a_wr)&&(fifo_a_wr_mask[3]))
|
fifo_a_mem_3[fifo_a_wr_addr] <= fifo_a_wr_data[31:24];
|
fifo_a_mem_3[fifo_a_wr_addr] <= fifo_a_wr_data[31:24];
|
|
|
fifo_b_wr <= 1'b0;
|
fifo_b_wr <= 1'b0;
|
fifo_b_wr_data <= { ll_out_dat, ll_out_dat, ll_out_dat, ll_out_dat };
|
fifo_b_wr_data <= { ll_out_dat, ll_out_dat, ll_out_dat, ll_out_dat };
|
if ((write_stb)&&(i_wb_addr[1:0]==2'b11))
|
if ((write_stb)&&(wb_addr[1:0]==2'b11))
|
begin
|
begin
|
fifo_b_wr <= 1'b1;
|
fifo_b_wr <= 1'b1;
|
fifo_b_wr_mask <= 4'b1111;
|
fifo_b_wr_mask <= 4'b1111;
|
fifo_b_wr_addr <= fifo_wb_addr;
|
fifo_b_wr_addr <= fifo_wb_addr;
|
fifo_b_wr_data <= i_wb_data;
|
fifo_b_wr_data <= wb_data;
|
end else if (pre_fifo_b_wr)
|
end else if (pre_fifo_b_wr)
|
begin
|
begin
|
fifo_b_wr <= 1'b1;
|
fifo_b_wr <= 1'b1;
|
fifo_b_wr_addr <= ll_fifo_addr[(LGFIFOLN+1):2];
|
fifo_b_wr_addr <= ll_fifo_addr[(LGFIFOLN+1):2];
|
case(ll_fifo_addr[1:0])
|
case(ll_fifo_addr[1:0])
|
| Line 771... |
Line 796... |
begin
|
begin
|
// Idle the channel
|
// Idle the channel
|
ll_fifo_rd_complete <= 1'b1;
|
ll_fifo_rd_complete <= 1'b1;
|
fifo_byte <= 8'hff;
|
fifo_byte <= 8'hff;
|
end
|
end
|
end else if ((write_stb)&&(i_wb_addr == `SDSPI_CMD_ADDRESS))
|
end else if ((write_stb)&&(wb_addr == `SDSPI_CMD_ADDRESS))
|
begin
|
begin
|
ll_fifo_pkt_state <= 3'h0;
|
ll_fifo_pkt_state <= 3'h0;
|
ll_fifo_rd_complete <= 1'b0;
|
ll_fifo_rd_complete <= 1'b0;
|
fifo_byte <= (i_wb_data[12]) ? fifo_b_byte : fifo_a_byte;
|
fifo_byte <= (wb_data[12]) ? fifo_b_byte : fifo_a_byte;
|
fifo_rd_crc_stb <= 1'b1;
|
fifo_rd_crc_stb <= 1'b1;
|
end else begin // Packet state is IDLE (clear the CRC registers)
|
end else begin // Packet state is IDLE (clear the CRC registers)
|
ll_fifo_pkt_state <= 3'b111;
|
ll_fifo_pkt_state <= 3'b111;
|
ll_fifo_rd_complete <= 1'b1;
|
ll_fifo_rd_complete <= 1'b1;
|
end
|
end
|
