| Line 52... |
Line 52... |
o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3, // Color LEDs
|
o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3, // Color LEDs
|
// RS232 UART
|
// RS232 UART
|
i_uart_rx, o_uart_tx,
|
i_uart_rx, o_uart_tx,
|
// Quad-SPI Flash control
|
// Quad-SPI Flash control
|
o_qspi_sck, o_qspi_cs_n, io_qspi_dat,
|
o_qspi_sck, o_qspi_cs_n, io_qspi_dat,
|
// Missing: Ethernet
|
// Ethernet
|
|
o_eth_rstn, o_eth_ref_clk,
|
|
i_eth_rx_clk, i_eth_col, i_eth_crs, i_eth_rx_dv, i_eth_rxd, i_eth_rxerr,
|
|
i_eth_tx_clk, o_eth_tx_en, o_eth_txd,
|
|
// Ethernet (MDIO)
|
o_eth_mdclk, io_eth_mdio,
|
o_eth_mdclk, io_eth_mdio,
|
// Memory
|
// Memory
|
ddr3_reset_n, ddr3_cke, ddr3_ck_p, ddr3_ck_n,
|
ddr3_reset_n, ddr3_cke, ddr3_ck_p, ddr3_ck_n,
|
ddr3_cs_n, ddr3_ras_n, ddr3_cas_n, ddr3_we_n,
|
ddr3_cs_n, ddr3_ras_n, ddr3_cas_n, ddr3_we_n,
|
ddr3_dqs_p, ddr3_dqs_n,
|
ddr3_dqs_p, ddr3_dqs_n,
|
| Line 82... |
Line 86... |
input i_uart_rx;
|
input i_uart_rx;
|
output wire o_uart_tx;
|
output wire o_uart_tx;
|
// Quad SPI flash
|
// Quad SPI flash
|
output wire o_qspi_sck, o_qspi_cs_n;
|
output wire o_qspi_sck, o_qspi_cs_n;
|
inout [3:0] io_qspi_dat;
|
inout [3:0] io_qspi_dat;
|
// Ethernet // Not yet implemented
|
// Ethernet
|
|
output wire o_eth_rstn, o_eth_ref_clk;
|
|
input i_eth_rx_clk, i_eth_col, i_eth_crs, i_eth_rx_dv;
|
|
input [3:0] i_eth_rxd;
|
|
input i_eth_rxerr;
|
|
input i_eth_tx_clk;
|
|
output wire o_eth_tx_en;
|
|
output [3:0] o_eth_txd;
|
// Ethernet control (MDIO)
|
// Ethernet control (MDIO)
|
output wire o_eth_mdclk;
|
output wire o_eth_mdclk;
|
inout wire io_eth_mdio;
|
inout wire io_eth_mdio;
|
// DDR3 SDRAM
|
// DDR3 SDRAM
|
output wire ddr3_reset_n;
|
output wire ddr3_reset_n;
|
| Line 116... |
Line 127... |
o_oled_pmoden;
|
o_oled_pmoden;
|
// Aux UART
|
// Aux UART
|
input i_aux_rx, i_aux_rts;
|
input i_aux_rx, i_aux_rts;
|
output wire o_aux_tx, o_aux_cts;
|
output wire o_aux_tx, o_aux_cts;
|
|
|
|
wire eth_tx_clk, eth_rx_clk;
|
|
`ifdef VERILATOR
|
|
wire s_clk, s_reset;
|
|
assign s_clk = sys_clk_i;
|
|
|
|
assign eth_tx_clk = i_eth_tx_clk;
|
|
assign eth_rx_clk = i_eth_rx_clk;
|
|
|
|
`else
|
// Build our master clock
|
// Build our master clock
|
wire s_clk, sys_clk, mem_clk_200mhz,
|
wire s_clk, sys_clk, mem_clk_200mhz,
|
clk1_unused, clk2_unused, enet_clk, clk4_unnused,
|
clk1_unused, clk2_unused, enet_clk, clk4_unnused,
|
clk5_unused, clk_feedback, clk_locked, mem_clk_200mhz_nobuf;
|
clk5_unused, clk_feedback, clk_locked, mem_clk_200mhz_nobuf;
|
PLLE2_BASE #(
|
PLLE2_BASE #(
|
| Line 128... |
Line 148... |
.CLKIN1_PERIOD(10.0), // Input clock period in ns resolution
|
.CLKIN1_PERIOD(10.0), // Input clock period in ns resolution
|
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: divide amount for each CLKOUT(1-128)
|
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: divide amount for each CLKOUT(1-128)
|
.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
|
.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
|
.CLKOUT0_DIVIDE(8), // 100 MHz (Clock for MIG)
|
.CLKOUT0_DIVIDE(8), // 100 MHz (Clock for MIG)
|
.CLKOUT1_DIVIDE(4), // 200 MHz (MIG Reference clock)
|
.CLKOUT1_DIVIDE(4), // 200 MHz (MIG Reference clock)
|
.CLKOUT2_DIVIDE(32), // 50 MHz (Unused)
|
.CLKOUT2_DIVIDE(16), // 50 MHz (Unused)
|
.CLKOUT3_DIVIDE(64), // 25 MHz (Unused/Ethernet clock)
|
.CLKOUT3_DIVIDE(32), // 25 MHz (Ethernet reference clk)
|
.CLKOUT4_DIVIDE(32), // 50 MHz (Unused clock?)
|
.CLKOUT4_DIVIDE(32), // 50 MHz (Unused clock?)
|
.CLKOUT5_DIVIDE(24), // 66 MHz
|
.CLKOUT5_DIVIDE(24), // 66 MHz
|
// CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT
|
// CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
| Line 169... |
Line 189... |
|
|
BUFH feedback_buffer(.I(clk_feedback),.O(clk_feedback_bufd));
|
BUFH feedback_buffer(.I(clk_feedback),.O(clk_feedback_bufd));
|
// BUFG memref_buffer(.I(mem_clk_200mhz_nobuf),.O(mem_clk_200mhz));
|
// BUFG memref_buffer(.I(mem_clk_200mhz_nobuf),.O(mem_clk_200mhz));
|
IBUF sysclk_buf(.I(sys_clk_i[0]), .O(sys_clk));
|
IBUF sysclk_buf(.I(sys_clk_i[0]), .O(sys_clk));
|
|
|
|
BUFG eth_rx(.I(i_eth_rx_clk), .O(eth_rx_clk));
|
|
// assign eth_rx_clk = i_eth_rx_clk;
|
|
|
|
|
|
BUFG eth_tx(.I(i_eth_tx_clk), .O(eth_tx_clk));
|
|
// assign eth_tx_clk = i_eth_tx_clk;
|
|
`endif
|
|
|
//
|
//
|
//
|
//
|
// UART interface
|
// UART interface
|
//
|
//
|
//
|
//
|
| Line 192... |
Line 220... |
// The first is the "PRE"-reset. This is a wire, set from the external
|
// The first is the "PRE"-reset. This is a wire, set from the external
|
// reset button. In good old-fashioned asynch-logic to synchronous
|
// reset button. In good old-fashioned asynch-logic to synchronous
|
// logic fashion, we synchronize this wire by registering it first
|
// logic fashion, we synchronize this wire by registering it first
|
// to pre_reset, and then to pwr_reset (the actual reset wire).
|
// to pre_reset, and then to pwr_reset (the actual reset wire).
|
//
|
//
|
|
wire s_reset; // Ultimate system reset wire
|
reg [7:0] pre_reset;
|
reg [7:0] pre_reset;
|
reg pwr_reset;
|
reg pwr_reset;
|
// Since all our stuff is synchronous to the clock that comes out of
|
// Since all our stuff is synchronous to the clock that comes out of
|
// the memory controller, sys_reset must needs come out of the memory
|
// the memory controller, sys_reset must needs come out of the memory
|
// controller.
|
// controller.
|
| Line 211... |
Line 240... |
// and then continues with the actual reset, now that we've
|
// and then continues with the actual reset, now that we've
|
// synchronized our reset button wire. This is an active LOW reset.
|
// synchronized our reset button wire. This is an active LOW reset.
|
initial pwr_reset = 1'b0;
|
initial pwr_reset = 1'b0;
|
always @(posedge sys_clk)
|
always @(posedge sys_clk)
|
pwr_reset <= pre_reset[7];
|
pwr_reset <= pre_reset[7];
|
|
`ifdef VERILATOR
|
|
assign s_reset = pwr_reset;
|
|
`else
|
//
|
//
|
// Of course, this only goes into the memory controller. The true
|
// Of course, this only goes into the memory controller. The true
|
// device reset comes out of that memory controller, synchronized to
|
// device reset comes out of that memory controller, synchronized to
|
// our memory generator provided clock(s)
|
// our memory generator provided clock(s)
|
|
`endif
|
|
|
wire w_ck_uart, w_uart_tx;
|
wire w_ck_uart, w_uart_tx;
|
rxuart rcv(s_clk, s_reset, bus_uart_setup, i_uart_rx,
|
rxuart rcv(s_clk, s_reset, bus_uart_setup, i_uart_rx,
|
rx_stb, rx_data, rx_break,
|
rx_stb, rx_data, rx_break,
|
rx_parity_err, rx_frame_err, w_ck_uart);
|
rx_parity_err, rx_frame_err, w_ck_uart);
|
| Line 284... |
Line 317... |
ram_cyc, ram_stb, ram_we, ram_addr, ram_wdata,
|
ram_cyc, ram_stb, ram_we, ram_addr, ram_wdata,
|
ram_ack, ram_stall, ram_rdata, ram_err,
|
ram_ack, ram_stall, ram_rdata, ram_err,
|
ram_dbg,
|
ram_dbg,
|
// SD Card
|
// SD Card
|
o_sd_sck, w_sd_cmd, w_sd_data, io_sd_cmd, io_sd, i_sd_cs,
|
o_sd_sck, w_sd_cmd, w_sd_data, io_sd_cmd, io_sd, i_sd_cs,
|
|
// Ethernet
|
|
o_eth_rstn,
|
|
eth_rx_clk, i_eth_col, i_eth_crs, i_eth_rx_dv,
|
|
i_eth_rxd, i_eth_rxerr,
|
|
eth_tx_clk, o_eth_tx_en, o_eth_txd,
|
// Ethernet control (MDIO) lines
|
// Ethernet control (MDIO) lines
|
o_eth_mdclk, w_mdio, w_mdwe, io_eth_mdio,
|
o_eth_mdclk, w_mdio, w_mdwe, io_eth_mdio,
|
// OLEDRGB PMod wires
|
// OLEDRGB PMod wires
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
o_oled_reset_n, o_oled_vccen, o_oled_pmoden,
|
o_oled_reset_n, o_oled_vccen, o_oled_pmoden,
|
| Line 320... |
Line 358... |
// ?? Dual mode out (not yet)
|
// ?? Dual mode out (not yet)
|
//
|
//
|
//
|
//
|
wire [3:0] i_qspi_pedge, i_qspi_nedge;
|
wire [3:0] i_qspi_pedge, i_qspi_nedge;
|
|
|
|
`ifdef VERILATOR
|
|
assign o_qspi_sck = w_qspi_sck;
|
|
assign o_qspi_cs_n = w_qspi_cs_n;
|
|
;
|
|
();
|
|
[*];
|
|
`else
|
xoddr xqspi_sck( s_clk, { w_qspi_sck, w_qspi_sck }, o_qspi_sck);
|
xoddr xqspi_sck( s_clk, { w_qspi_sck, w_qspi_sck }, o_qspi_sck);
|
xoddr xqspi_csn( s_clk, { w_qspi_cs_n, w_qspi_cs_n },o_qspi_cs_n);
|
xoddr xqspi_csn( s_clk, { w_qspi_cs_n, w_qspi_cs_n },o_qspi_cs_n);
|
//
|
//
|
xioddr xqspi_d0( s_clk, (qspi_bmod != 2'b11),
|
xioddr xqspi_d0( s_clk, (qspi_bmod != 2'b11),
|
{ qspi_dat[0], qspi_dat[0] },
|
{ qspi_dat[0], qspi_dat[0] },
|
| Line 335... |
Line 380... |
(qspi_bmod[1])?{ qspi_dat[2], qspi_dat[2] }:2'b11,
|
(qspi_bmod[1])?{ qspi_dat[2], qspi_dat[2] }:2'b11,
|
{ i_qspi_pedge[2], i_qspi_nedge[2] }, io_qspi_dat[2]);
|
{ i_qspi_pedge[2], i_qspi_nedge[2] }, io_qspi_dat[2]);
|
xioddr xqspi_d3( s_clk, (qspi_bmod!=2'b11),
|
xioddr xqspi_d3( s_clk, (qspi_bmod!=2'b11),
|
(qspi_bmod[1])?{ qspi_dat[3], qspi_dat[3] }:2'b11,
|
(qspi_bmod[1])?{ qspi_dat[3], qspi_dat[3] }:2'b11,
|
{ i_qspi_pedge[3], i_qspi_nedge[3] }, io_qspi_dat[3]);
|
{ i_qspi_pedge[3], i_qspi_nedge[3] }, io_qspi_dat[3]);
|
|
`endif
|
|
reg [3:0] r_qspi_dat;
|
|
always @(posedge s_clk)
|
|
r_qspi_dat <= i_qspi_pedge;
|
|
assign i_qspi_dat = r_qspi_dat;
|
|
|
assign i_qspi_dat = i_qspi_pedge;
|
|
//
|
//
|
// Proposed QSPI mode select, to allow dual I/O mode
|
// Proposed QSPI mode select, to allow dual I/O mode
|
// 000 Normal SPI mode
|
// 000 Normal SPI mode
|
// 001 Dual mode input
|
// 001 Dual mode input
|
// 010 Dual mode, output
|
// 010 Dual mode, output
|
| Line 350... |
Line 399... |
//
|
//
|
|
|
|
|
//
|
//
|
//
|
//
|
|
// Generate a reference clock for the network
|
|
//
|
|
//
|
|
`ifdef VERILATOR
|
|
assign o_eth_ref_clk = i_eth_tx_clk;
|
|
`else
|
|
xoddr e_ref_clk( enet_clk, { 1'b1, 1'b0 }, o_eth_ref_clk );
|
|
`endif
|
|
|
|
//
|
|
//
|
// Wires for setting up the SD Card Controller
|
// Wires for setting up the SD Card Controller
|
//
|
//
|
//
|
//
|
assign io_sd_cmd = w_sd_cmd ? 1'bz:1'b0;
|
assign io_sd_cmd = w_sd_cmd ? 1'bz:1'b0;
|
assign io_sd[0] = w_sd_data[0]? 1'bz:1'b0;
|
assign io_sd[0] = w_sd_data[0]? 1'bz:1'b0;
|
| Line 373... |
Line 433... |
//
|
//
|
//
|
//
|
// Now, to set up our memory ...
|
// Now, to set up our memory ...
|
//
|
//
|
//
|
//
|
migsdram rami(
|
migsdram #(.AXIDWIDTH(5)) rami(
|
.i_clk(mem_clk_nobuf), .i_clk_200mhz(mem_clk_200mhz_nobuf),
|
.i_clk(mem_clk_nobuf), .i_clk_200mhz(mem_clk_200mhz_nobuf),
|
.o_sys_clk(s_clk), .i_rst(pwr_reset), .o_sys_reset(s_reset),
|
.o_sys_clk(s_clk), .i_rst(pwr_reset), .o_sys_reset(s_reset),
|
.i_wb_cyc(ram_cyc), .i_wb_stb(ram_stb), .i_wb_we(ram_we),
|
.i_wb_cyc(ram_cyc), .i_wb_stb(ram_stb), .i_wb_we(ram_we),
|
.i_wb_addr(ram_addr), .i_wb_data(ram_wdata),
|
.i_wb_addr(ram_addr), .i_wb_data(ram_wdata),
|
.i_wb_sel(4'hf),
|
.i_wb_sel(4'hf),
|
