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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbddrsdram.v
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// Filename: wbddrsdram.v
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//
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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// Project: A wishbone controlled DDR3 SDRAM memory controller.
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// Used in: OpenArty, an entirely open SoC based upon the Arty platform
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//
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//
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// Purpose:
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// Purpose: To control a DDR3-1333 (9-9-9) memory from a wishbone bus.
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// In our particular implementation, there will be two command
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// clocks (2.5 ns) per FPGA clock (i_clk) at 5 ns, and 64-bits transferred
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// per FPGA clock. However, since the memory is focused around 128-bit
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// word transfers, attempts to transfer other than adjacent 64-bit words
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// will (of necessity) suffer stalls. Please see the documentation for
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// more details of how this controller works.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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`define DDR_WEBIT 17
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`define DDR_WEBIT 17
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`define DDR_NOPTIMER 16 // Steal this from BA bits
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`define DDR_NOPTIMER 16 // Steal this from BA bits
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`define DDR_BABITS 3 // BABITS are really from 18:16, they are 3 bits
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`define DDR_BABITS 3 // BABITS are really from 18:16, they are 3 bits
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`define DDR_ADDR_BITS 14
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`define DDR_ADDR_BITS 14
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//
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//
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//
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module wbddrsdram(i_clk, i_reset,
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module wbddrsdram(i_clk, i_reset,
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// Wishbone inputs
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_sel,
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// Wishbone outputs
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_ddr_reset_n, o_ddr_cke,
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// Memory command wires
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_reset_n, o_ddr_cke, o_ddr_bus_oe,
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o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_oe,
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o_ddr_cmd_a, o_ddr_cmd_b,
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o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
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// And the data wires to go with them ....
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parameter CKRBITS = 13, // Bits in CKREFI4
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o_ddr_data, i_ddr_data);
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CKREFI = 13'd1560, // 4 * 7.8us at 200 MHz clock
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// These parameters are not really meant for adjusting from the
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CKRFC = 320,
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// top level. These are more internal variables, recorded here
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CKWR = 3,
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// so that things can be automatically adjusted without much
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CKRP = 11, // (=tRTP)Time from precharge to open command
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// problem.
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CKCAS = 11, // CAS Latency, tCL
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parameter CKRP = 3;
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CKXPR = CKRFC+5+2, // Clocks per tXPR timeout
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parameter BUSNOW = 4, BUSREG = BUSNOW-1;
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BUSREG= 2+CKCAS,
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// The commands (above) include (in this order):
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BUSNOW= 3+CKCAS;
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// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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input i_clk, i_reset;
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// o_ddr_dqs, o_ddr_dm, o_ddr_odt
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input i_clk, // *MUST* be at 200 MHz for this to work
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i_reset;
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [25:0] i_wb_addr;
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input [24:0] i_wb_addr; // Identifies a 64-bit word of interest
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input [31:0] i_wb_data;
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input [63:0] i_wb_data;
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// Wishbone outputs
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input [7:0] i_wb_sel;
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output reg o_wb_ack;
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// Wishbone responses/outputs
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output reg o_wb_stall;
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output reg o_wb_ack, o_wb_stall;
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output reg [31:0] o_wb_data;
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output reg [63:0] o_wb_data;
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// DDR3 RAM Controller
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// DDR memory command wires
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output reg o_ddr_reset_n, o_ddr_cke;
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output reg o_ddr_reset_n, o_ddr_cke, o_ddr_bus_oe;
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// Control outputs
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// CMDs are:
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output wire o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
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// 4 bits of CS, RAS, CAS, WE
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// DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow
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// 3 bits of bank
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output wire o_ddr_dqs;
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// 14 bits of Address
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output reg o_ddr_dm;
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// 1 bit of DQS (strobe active, or not)
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output reg o_ddr_odt;
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// 4 bits of mask (one per byte)
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output wire o_ddr_bus_oe;
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// 1 bit of ODT
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// Address outputs
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// ----
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output wire [13:0] o_ddr_addr;
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// 27 bits total
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output wire [2:0] o_ddr_ba;
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output wire [26:0] o_ddr_cmd_a, o_ddr_cmd_b;
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// And the data inputs and outputs
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output reg [63:0] o_ddr_data;
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output reg [31:0] o_ddr_data;
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input [63:0] i_ddr_data;
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input [31:0] i_ddr_data;
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reg drive_dqs;
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// The pending transaction
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reg [31:0] r_data;
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reg r_pending, r_we;
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reg [25:0] r_addr;
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reg [13:0] r_row;
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reg [2:0] r_bank;
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reg [9:0] r_col;
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reg [1:0] r_sub;
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reg r_move; // It was accepted, and can move to next stage
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// The pending transaction, one further into the pipeline. This is
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// the stage where the read/write command is actually given to the
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// interface if we haven't stalled.
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reg [31:0] s_data;
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reg s_pending, s_we; // , s_match;
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reg [25:0] s_addr;
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reg [13:0] s_row, s_nxt_row;
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reg [2:0] s_bank, s_nxt_bank;
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reg [9:0] s_col;
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reg [1:0] s_sub;
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// Can the pending transaction be satisfied with the current (ongoing)
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// transaction?
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reg m_move, m_match, m_pending, m_we;
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reg [25:0] m_addr;
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reg [13:0] m_row;
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reg [2:0] m_bank;
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reg [9:0] m_col;
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reg [1:0] m_sub;
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// Can we preload the next bank?
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reg [13:0] r_nxt_row;
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reg [2:0] r_nxt_bank;
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reg need_close_bank, need_close_this_bank,
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//////////
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last_close_bank, maybe_close_next_bank,
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last_maybe_close,
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need_open_bank, last_open_bank, maybe_open_next_bank,
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last_maybe_open,
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valid_bank, last_valid_bank;
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reg [(`DDR_CMDLEN-1):0] close_bank_cmd, activate_bank_cmd,
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maybe_close_cmd, maybe_open_cmd, rw_cmd;
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reg [1:0] rw_sub;
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reg rw_we;
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wire w_this_closing_bank, w_this_opening_bank,
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w_this_maybe_close, w_this_maybe_open,
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w_this_rw_move;
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reg last_closing_bank, last_opening_bank;
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wire w_need_close_this_bank, w_need_open_bank,
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w_r_valid, w_s_valid, w_s_match;
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//
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//
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// tWTR = 7.5
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// tRRD = 7.5
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// tREFI= 7.8
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// tFAW = 45
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// tRTP = 7.5
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// tCKE = 5.625
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// tRFC = 160
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// tRP = 13.5
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// tRAS = 36
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// tRCD = 13.5
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//
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// RESET:
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// 1. Hold o_reset_n = 1'b0; for 200 us, or 40,000 clocks (65536 perhaps?)
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// Hold cke low during this time as well
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// The clock should be free running into the chip during this time
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// Leave command in NOOP state: {cs,ras,cas,we} = 4'h7;
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// ODT must be held low
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// 2. Hold cke low for another 500us, or 100,000 clocks
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// 3. Raise CKE, continue outputting a NOOP for
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// tXPR, tDLLk, and tZQInit
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// 4. Load MRS2, wait tMRD
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// 4. Load MRS3, wait tMRD
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// 4. Load MRS1, wait tMOD
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// Before using the SDRAM, we'll need to program at least 3 of the mode
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// registers, if not all 4.
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// tMOD clocks are required to program the mode registers, during which
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// time the RAM must be idle.
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//
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//
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// NOOP: CS low, RAS, CAS, and WE high
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// Reset Logic
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//
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//
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//////////
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//
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//
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//
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// Reset logic should be simple, and is given as follows:
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// Reset logic should be simple, and is given as follows:
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// note that it depends upon a ROM memory, reset_mem, and an address into that
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// note that it depends upon a ROM memory, reset_mem, and an address into that
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// memory: reset_address. Each memory location provides either a "command" to
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// memory: reset_address. Each memory location provides either a "command" to
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// the DDR3 SDRAM, or a timer to wait until the next command. Further, the
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// the DDR3 SDRAM, or a timer to wait until the next command. Further, the
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// timer commands indicate whether or not the command during the timer is to
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// timer commands indicate whether or not the command during the timer is to
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// be set to idle, or whether the command is instead left as it was.
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// be set to idle, or whether the command is instead left as it was.
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reg reset_override, reset_ztimer, maintenance_override;
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reg reset_override, reset_ztimer, maintenance_override;
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reg [4:0] reset_address;
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reg [4:0] reset_address;
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reg [(`DDR_CMDLEN-1):0] reset_cmd, cmd, refresh_cmd,
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reg [(`DDR_CMDLEN-1):0] reset_cmd, cmd_a, cmd_b, refresh_cmd,
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maintenance_cmd;
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maintenance_cmd;
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reg [24:0] reset_instruction;
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reg [24:0] reset_instruction;
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reg [16:0] reset_timer;
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reg [16:0] reset_timer;
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initial reset_override = 1'b1;
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initial reset_override = 1'b1;
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initial reset_address = 5'h0;
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initial reset_address = 5'h0;
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Line 174... |
begin
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begin
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reset_ztimer <= 1'b0;
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reset_ztimer <= 1'b0;
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reset_timer <= reset_instruction[16:0];
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reset_timer <= reset_instruction[16:0];
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end
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end
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wire [16:0] w_ckXPR, w_ckRST, w_ckRP,
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wire [16:0] w_ckXPR, w_ckRFC_first;
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w_ckRFC_first;
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wire [2:0] w_ckCAS_MR2, w_ckCAS_MR0, w_ckCAS, w_ckFIVE;
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wire [13:0] w_MR0, w_MR1, w_MR2;
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wire [13:0] w_MR0, w_MR1, w_MR2;
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assign w_ckXPR = CKXPR;
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assign w_MR0 = 14'h0420;
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assign w_ckRST = 4;
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assign w_MR1 = 14'h0044;
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assign w_ckRP = CKRP-2;
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assign w_MR2 = 14'h0040;
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/* verilator lint_off WIDTH */
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assign w_ckXPR = 17'd68; // Table 68, p186
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assign w_ckCAS = CKCAS;
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assign w_ckRFC_first = 17'd30; // i.e. 64 nCK, or ckREFI
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/* verilator lint_on WIDTH */
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assign w_ckRFC_first = CKRFC-2-9+8;
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assign w_ckFIVE = 3'h5;
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assign w_ckCAS_MR2 = w_ckFIVE-3'h5; // w_ckCAS-3'h5;
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assign w_ckCAS_MR0 = w_ckFIVE-3'h4; // w_ckCAS-3'h4;
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assign w_MR2 = { 3'h0, 2'b00, 1'b0, 1'b0, 1'b1, w_ckCAS_MR2, 3'b0 };
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assign w_MR1 = {
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1'h0, // Reserved for Future Use (RFU)
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1'b0, // Qoff - output buffer enabled
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1'b1, // TDQS ... enabled
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1'b0, // RFU
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1'b0, // High order bit, Rtt_Nom (3'b011)
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1'b0, // RFU
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//
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1'b0, // Disable write-leveling
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1'b1, // Mid order bit of Rtt_Nom
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1'b0, // High order bit of Output Drvr Impedence Ctrl
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2'b0, // Additive latency = 0
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1'b1, // Low order bit of Rtt_Nom
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1'b0, // DIC set to 2'b00
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1'b0 // MRS1, DLL enable
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};
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assign w_MR0 = {
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1'b0, // Reserved for future use
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1'b0, // PPD control, (slow exit(DLL off))
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3'b1, // Write recovery for auto precharge
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1'b0, // DLL Reset (No)
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//
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1'b0, // TM mode normal
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w_ckCAS_MR0, // High 3-bits, CAS latency (=4'b1110=4'd5,tCL=11)
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//
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1'b0, // Read burst type = nibble sequential
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(CKCAS>11)? 1'b1:1'b0, // Low bit of cas latency
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2'b0 // Burst length = 8 (Fixed)
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};
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always @(posedge i_clk)
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always @(posedge i_clk)
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// DONE, TIMER, RESET, CKE,
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if (i_reset)
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if (i_reset)
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reset_instruction <= { 4'h4, `DDR_NOOP, 17'd40_000 };
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reset_instruction <= { 4'h4, `DDR_NOOP, 17'd40_000 };
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else if (reset_ztimer) case(reset_address) // RSTDONE, TIMER, CKE, ??
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else if (reset_ztimer) case(reset_address) // RSTDONE, TIMER, CKE, ??
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// 1. Reset asserted (active low) for 200 us. (@200MHz)
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// 1. Reset asserted (active low) for 200 us. (@200MHz)
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5'h0: reset_instruction <= { 4'h4, `DDR_NOOP, 17'd40_000 };
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5'h0: reset_instruction <= { 4'h4, `DDR_NOOP, 17'd40_000 };
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// 2. Reset de-asserted, wait 500 us before asserting CKE
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// 2. Reset de-asserted, wait 500 us before asserting CKE
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5'h1: reset_instruction <= { 4'h6, `DDR_NOOP, 17'd100_000 };
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5'h1: reset_instruction <= { 4'h6, `DDR_NOOP, 17'd100_000 };
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// 3. Assert CKE, wait minimum of Reset CKE Exit time
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// 3. Assert CKE, wait minimum of Reset CKE Exit time
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5'h2: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckXPR };
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5'h2: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckXPR };
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// 4. Look MR2. (1CK, no TIMER)
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// 4. Set MR2. (4 nCK, no TIMER, but needs a NOOP cycle)
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5'h3: reset_instruction <= { 4'h3, `DDR_NOOP, 3'h2, w_MR2 };
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5'h3: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h2, w_MR2 };
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5'h4: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h2, w_MR2 };
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5'h4: reset_instruction <= { 4'h3, `DDR_NOOP, 17'h00 };
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5'h5: reset_instruction <= { 4'h3, `DDR_NOOP, 3'h2, w_MR2 };
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// 5. Set MR1. (4 nCK, no TIMER, but needs a NOOP cycle)
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// 3. Wait 4 clocks (tMRD)
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5'h5: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h1, w_MR1 };
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5'h6: reset_instruction <= { 4'h7, `DDR_NOOP, 17'h02 };
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5'h6: reset_instruction <= { 4'h3, `DDR_NOOP, 17'h00 };
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// 5. Set MR1
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// 6. Set MR0
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5'h7: reset_instruction <= { 4'h3, `DDR_NOOP, 3'h1, w_MR1 };
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5'h7: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h0, w_MR0 };
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5'h8: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h1, w_MR1 };
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// 7. Wait 12 clocks
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5'h9: reset_instruction <= { 4'h3, `DDR_NOOP, 3'h1, w_MR1 };
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5'h8: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd10 };
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// 7. Wait another 4 clocks
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// 8. Issue a ZQCL command to start ZQ calibration, A10 is high
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5'ha: reset_instruction <= { 4'h7, `DDR_NOOP, 17'h02 };
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5'h9: reset_instruction <= { 4'h3, `DDR_ZQS, 6'h0, 1'b1, 10'h0};
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// 8. Send MRS0
|
//11.Wait for both tDLLK and tZQinit completed, both are
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5'hb: reset_instruction <= { 4'h3, `DDR_NOOP, 3'h0, w_MR0 };
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// 512 cks. Of course, since every one of these commands takes
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5'hc: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h0, w_MR0 };
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// two clocks, we wait for half as many clocks (minus two for
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5'hd: reset_instruction <= { 4'h3, `DDR_NOOP, 3'h0, w_MR0 };
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// our timer logic)
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// 9. Wait tMOD, is max(12 clocks, 15ns)
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5'ha: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd254 };
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5'he: reset_instruction <= { 4'h7, `DDR_NOOP, 17'h0a };
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// 10. Issue a ZQCL command to start ZQ calibration, A10 is high
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5'hf: reset_instruction <= { 4'h3, `DDR_ZQS, 6'h0, 1'b1, 10'h0};
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//11.Wait for both tDLLK and tZQinit completed, both are 512 cks
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5'h10: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd512 };
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// 12. Precharge all command
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// 12. Precharge all command
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5'h11: reset_instruction <= { 4'h3, `DDR_PRECHARGE, 6'h0, 1'b1, 10'h0 };
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5'hb: reset_instruction <= { 4'h3, `DDR_PRECHARGE, 6'h0, 1'b1, 10'h0 };
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// 13. Wait for the precharge to complete
|
// 13. Wait for the precharge to complete. A count of one,
|
5'h12: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckRP };
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// will have us waiting (1+2)*2 or 6 clocks, so we should be
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|
// good here.
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5'hc: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd1 };
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// 14. A single Auto Refresh commands
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// 14. A single Auto Refresh commands
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5'h13: reset_instruction <= { 4'h3, `DDR_REFRESH, 17'h00 };
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5'hd: reset_instruction <= { 4'h3, `DDR_REFRESH, 17'h00 };
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// 15. Wait for the auto refresh to complete
|
// 15. Wait for the auto refresh to complete
|
5'h14: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckRFC_first };
|
5'he: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckRFC_first };
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// Two Auto Refresh commands
|
|
default:
|
default:
|
reset_instruction <={4'hb, `DDR_NOOP, 17'd00_000 };
|
reset_instruction <={4'hb, `DDR_NOOP, 17'd00_000 };
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endcase
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endcase
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// reset_instruction <= reset_mem[reset_address];
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|
|
|
initial reset_address = 5'h0;
|
initial reset_address = 5'h0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_reset)
|
if (i_reset)
|
reset_address <= 5'h1;
|
reset_address <= 5'h1;
|
else if ((reset_ztimer)&&(reset_override))
|
else if ((reset_ztimer)&&(reset_override))
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reset_address <= reset_address + 5'h1;
|
reset_address <= reset_address + 5'h1;
|
//
|
|
// initial reset_mem =
|
|
// 0. !DONE, TIMER,RESET_N=0, CKE=0, CMD = NOOP, TIMER = 200us ( 40,000)
|
|
// 1. !DONE, TIMER,RESET_N=1, CKE=0, CMD = NOOP, TIMER = 500us (100,000)
|
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// 2. !DONE, TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = (Look me up)
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// 3. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS
|
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// 4. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
|
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// 5. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS3
|
|
// 6. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
|
|
// 7. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS1
|
|
// 8. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
|
|
// 9. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS1
|
|
// 10. !DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMOD
|
|
// 11. !DONE,!TIMER,RESET_N=1, CKE=1, (Pre-charge all)
|
|
// 12. !DONE,!TIMER,RESET_N=1, CKE=1, (wait)
|
|
// 13. !DONE,!TIMER,RESET_N=1, CKE=1, (Auto-refresh)
|
|
// 14. !DONE,!TIMER,RESET_N=1, CKE=1, (Auto-refresh)
|
|
// 15. !DONE,!TIMER,RESET_N=1, CKE=1, (wait)
|
|
|
|
|
|
|
//////////
|
//
|
//
|
//
|
//
|
// Let's keep track of any open banks. There are 8 of them to keep track of.
|
// Refresh Logic
|
|
//
|
//
|
//
|
// A precharge requires 3 clocks at 200MHz to complete, 2 clocks at 100MHz.
|
//////////
|
//
|
//
|
//
|
//
|
//
|
//
|
|
// Okay, let's investigate when we need to do a refresh. Our plan will be to
|
|
// do a single refreshes every tREFI seconds. We will not push off refreshes,
|
|
// nor pull them in--for simplicity. tREFI = 7.8us, but it is a parameter
|
|
// in the number of clocks. In our case, 7.8us / 5ns = 1560 clocks (not nCK!)
|
|
//
|
|
// Note that 160ns are needed between refresh commands (JEDEC, p172), or
|
|
// 32 clocks @200MHz. After this time, no more refreshes will be needed for
|
|
// (1560-32) clocks (@ 200 MHz).
|
|
//
|
|
// This logic is very similar to the refresh logic, both use a memory as a
|
|
// script.
|
|
//
|
reg need_refresh;
|
reg need_refresh;
|
|
reg refresh_ztimer;
|
|
reg [16:0] refresh_counter;
|
|
reg [2:0] refresh_addr;
|
|
reg [23:0] refresh_instruction;
|
|
always @(posedge i_clk)
|
|
if (reset_override)
|
|
refresh_addr <= 3'hf;
|
|
else if (refresh_ztimer)
|
|
refresh_addr <= refresh_addr + 3'h1;
|
|
else if (refresh_instruction[`DDR_RFBEGIN])
|
|
refresh_addr <= 3'h0;
|
|
|
|
always @(posedge i_clk)
|
|
if (reset_override)
|
|
begin
|
|
refresh_ztimer <= 1'b1;
|
|
refresh_counter <= 17'd0;
|
|
end else if (!refresh_ztimer)
|
|
begin
|
|
refresh_ztimer <= (refresh_counter == 17'h1);
|
|
refresh_counter <= (refresh_counter - 17'h1);
|
|
end else if (refresh_instruction[`DDR_RFTIMER])
|
|
begin
|
|
refresh_ztimer <= 1'b0;
|
|
refresh_counter <= refresh_instruction[16:0];
|
|
end
|
|
|
|
wire [16:0] w_ckREFI;
|
|
assign w_ckREFI = 17'd1560; // == 6240/4
|
|
|
|
wire [16:0] w_ckREFI_left, w_ckRFC_nxt, w_wait_for_idle,
|
|
w_precharge_to_refresh;
|
|
|
|
// We need to wait for the bus to become idle from whatever state
|
|
// it is in. The difficult time for this measurement is assuming
|
|
// a write was just given. In that case, we need to wait for the
|
|
// write to complete, and then to wait an additional tWR (write
|
|
// recovery time) or 6 nCK clocks from the end of the write. This
|
|
// works out to seven idle bus cycles from the time of the write
|
|
// command, or a count of 5 (7-2).
|
|
assign w_wait_for_idle = 17'd5; //
|
|
assign w_precharge_to_refresh = 17'd1; // = 3-2
|
|
assign w_ckREFI_left[16:0] = 17'd1560 // The full interval
|
|
-17'd32 // Min what we've already waited
|
|
-w_wait_for_idle
|
|
-w_precharge_to_refresh-17'd12;
|
|
assign w_ckRFC_nxt[16:0] = 17'd32-17'd2;
|
|
|
|
always @(posedge i_clk)
|
|
if (refresh_ztimer)
|
|
case(refresh_addr)//NEED-REFRESH, HAVE-TIMER, BEGIN(start-over)
|
|
// First, a number of clocks needing no refresh
|
|
3'h0: refresh_instruction <= { 3'h2, `DDR_NOOP, w_ckREFI_left };
|
|
// Then, we take command of the bus and wait for it to be
|
|
// guaranteed idle
|
|
3'h1: refresh_instruction <= { 3'h6, `DDR_NOOP, w_wait_for_idle };
|
|
// Once the bus is idle, all commands complete, and a minimum
|
|
// recovery time given, we can issue a precharge all command
|
|
3'h2: refresh_instruction <= { 3'h4, `DDR_PRECHARGE, 17'h0400 };
|
|
// Now we need to wait tRP = 3 clocks (6 nCK)
|
|
3'h3: refresh_instruction <= { 3'h6, `DDR_NOOP, w_precharge_to_refresh };
|
|
3'h4: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
|
3'h5: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC_nxt };
|
|
default:
|
|
refresh_instruction <= { 3'h1, `DDR_NOOP, 17'h00 };
|
|
endcase
|
|
|
|
// Note that we don't need to check if (reset_override) here since
|
|
// refresh_ztimer will always be true if (reset_override)--in other
|
|
// words, it will be true for many, many, clocks--enough for this
|
|
// logic to settle out.
|
|
always @(posedge i_clk)
|
|
if (refresh_ztimer)
|
|
refresh_cmd <= refresh_instruction[20:0];
|
|
always @(posedge i_clk)
|
|
if (refresh_ztimer)
|
|
need_refresh <= refresh_instruction[`DDR_NEEDREFRESH];
|
|
|
|
|
|
/*
|
|
input i_clk, i_reset;
|
|
// Wishbone inputs
|
|
input i_wb_cyc, i_wb_stb, i_wb_we;
|
|
input [25:0] i_wb_addr;
|
|
input [31:0] i_wb_data;
|
|
// Wishbone outputs
|
|
output reg o_wb_ack;
|
|
output reg o_wb_stall;
|
|
output reg [31:0] o_wb_data;
|
|
// DDR3 RAM Controller
|
|
output reg o_ddr_reset_n, o_ddr_cke;
|
|
// Control outputs
|
|
output wire o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
|
|
// DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow
|
|
output wire o_ddr_dqs;
|
|
output reg o_ddr_odt;
|
|
output wire o_ddr_bus_oe;
|
|
// Address outputs
|
|
output wire [13:0] o_ddr_addr;
|
|
output wire [2:0] o_ddr_ba;
|
|
// And the data inputs and outputs
|
|
output reg [31:0] o_ddr_data;
|
|
input [31:0] i_ddr_data;
|
|
*/
|
|
|
|
|
|
reg [1:0] drive_dqs;
|
|
// Our chosen timing doesn't require any more resolution than one
|
|
// bus clock for ODT. (Of course, this really isn't necessary, since
|
|
// we aren't using ODT as per the MRx registers ... but we keep it
|
|
// around in case we change our minds later.)
|
|
reg ddr_odt;
|
|
reg [7:0] ddr_dm;
|
|
|
|
// The pending transaction
|
|
reg [63:0] r_data;
|
|
reg r_pending, r_we;
|
|
reg [24:0] r_addr;
|
|
reg [13:0] r_row;
|
|
reg [2:0] r_bank;
|
|
reg [9:0] r_col;
|
|
reg r_sub;
|
|
reg [7:0] r_sel;
|
|
|
|
// The pending transaction, one further into the pipeline. This is
|
|
// the stage where the read/write command is actually given to the
|
|
// interface if we haven't stalled.
|
|
reg [63:0] s_data;
|
|
reg s_pending, s_we; // , s_match;
|
|
reg [24:0] s_addr;
|
|
reg [13:0] s_row, s_nxt_row;
|
|
reg [2:0] s_bank, s_nxt_bank;
|
|
reg [9:0] s_col;
|
|
reg s_sub;
|
|
reg [7:0] s_sel;
|
|
|
|
// Can the pending transaction be satisfied with the current (ongoing)
|
|
// transaction?
|
|
reg m_move, m_match, m_pending, m_we;
|
|
reg [24:0] m_addr;
|
|
reg [13:0] m_row;
|
|
reg [2:0] m_bank;
|
|
reg [9:0] m_col;
|
|
reg [1:0] m_sub;
|
|
|
|
// Can we preload the next bank?
|
|
reg [13:0] r_nxt_row;
|
|
reg [2:0] r_nxt_bank;
|
|
|
|
reg need_close_bank, need_close_this_bank,
|
|
last_close_bank, maybe_close_next_bank,
|
|
last_maybe_close,
|
|
need_open_bank, last_open_bank, maybe_open_next_bank,
|
|
last_maybe_open,
|
|
valid_bank;
|
|
reg [(`DDR_CMDLEN-1):0] close_bank_cmd, activate_bank_cmd,
|
|
maybe_close_cmd, maybe_open_cmd, rw_cmd;
|
|
reg rw_sub;
|
|
reg rw_we;
|
|
|
|
wire w_this_closing_bank, w_this_opening_bank,
|
|
w_this_maybe_close, w_this_maybe_open,
|
|
w_this_rw_move;
|
|
reg last_closing_bank, last_opening_bank;
|
|
wire w_need_close_this_bank, w_need_open_bank,
|
|
w_r_valid, w_s_valid, w_s_match;
|
|
|
|
//////////
|
|
//
|
|
//
|
|
// Open Banks
|
|
//
|
|
//
|
|
//////////
|
|
//
|
|
//
|
|
//
|
|
// Let's keep track of any open banks. There are 8 of them to keep track of.
|
|
//
|
|
// A precharge requires 3 clocks at 200MHz to complete.
|
|
// An activate also requires 3 clocks at 200MHz to complete.
|
|
// Precharges are not allowed until the maximum of:
|
|
// 2 clocks (200 MHz) after a read command
|
|
// 8 clocks after a write command
|
|
//
|
|
//
|
wire w_precharge_all;
|
wire w_precharge_all;
|
reg [CKRP:0] bank_status [0:7];
|
reg [CKRP:0] bank_status [0:7];
|
reg [13:0] bank_address [0:7];
|
reg [13:0] bank_address [0:7];
|
reg [3:0] bank_wr_ck [0:7]; // tWTR
|
reg [3:0] bank_wr_ck [0:7]; // tWTR
|
reg bank_wr_ckzro [0:7]; // tWTR
|
reg bank_wr_ckzro [0:7]; // tWTR
|
reg [7:0] bank_open;
|
reg [7:0] bank_open;
|
reg [7:0] bank_closed;
|
reg [7:0] bank_closed;
|
|
|
wire [3:0] write_recycle_clocks;
|
wire [3:0] write_recycle_clocks;
|
assign write_recycle_clocks = CKWR+4+4;
|
assign write_recycle_clocks = 4'h8;
|
|
|
initial bank_open = 0;
|
initial bank_open = 0;
|
initial bank_closed = 8'hff;
|
initial bank_closed = 8'hff;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
| Line 445... |
Line 520... |
end else if (need_close_bank)
|
end else if (need_close_bank)
|
begin
|
begin
|
bank_status[close_bank_cmd[16:14]]
|
bank_status[close_bank_cmd[16:14]]
|
<= { bank_status[close_bank_cmd[16:14]][(CKRP-1):0], 1'b0 };
|
<= { bank_status[close_bank_cmd[16:14]][(CKRP-1):0], 1'b0 };
|
bank_open[close_bank_cmd[16:14]] <= 1'b0;
|
bank_open[close_bank_cmd[16:14]] <= 1'b0;
|
// bank_status[close_bank_cmd[16:14]][0] <= 1'b0;
|
|
end else if (need_open_bank)
|
end else if (need_open_bank)
|
begin
|
begin
|
bank_status[activate_bank_cmd[16:14]]
|
bank_status[activate_bank_cmd[16:14]]
|
<= { bank_status[activate_bank_cmd[16:14]][(CKRP-1):0], 1'b1 };
|
<= { bank_status[activate_bank_cmd[16:14]][(CKRP-1):0], 1'b1 };
|
// bank_status[activate_bank_cmd[16:14]][0] <= 1'b1;
|
|
bank_closed[activate_bank_cmd[16:14]] <= 1'b0;
|
bank_closed[activate_bank_cmd[16:14]] <= 1'b0;
|
end else if (valid_bank)
|
end else if (valid_bank)
|
;
|
; // Read/write command was issued. This neither opens
|
|
// nor closes any banks, and hence it needs no logic
|
|
// here
|
else if (maybe_close_next_bank)
|
else if (maybe_close_next_bank)
|
begin
|
begin
|
bank_status[maybe_close_cmd[16:14]]
|
bank_status[maybe_close_cmd[16:14]]
|
<= { bank_status[maybe_close_cmd[16:14]][(CKRP-1):0], 1'b0 };
|
<= { bank_status[maybe_close_cmd[16:14]][(CKRP-1):0], 1'b0 };
|
bank_open[maybe_close_cmd[16:14]] <= 1'b0;
|
bank_open[maybe_close_cmd[16:14]] <= 1'b0;
|
end else if (maybe_open_next_bank)
|
end else if (maybe_open_next_bank)
|
begin
|
begin
|
bank_status[maybe_open_cmd[16:14]]
|
bank_status[maybe_open_cmd[16:14]]
|
<= { bank_status[maybe_open_cmd[16:14]][(CKRP-1):0], 1'b1 };
|
<= { bank_status[maybe_open_cmd[16:14]][(CKRP-1):0], 1'b1 };
|
// bank_status[activate_bank_cmd[16:14]][0] <= 1'b1;
|
|
bank_closed[maybe_open_cmd[16:14]] <= 1'b0;
|
bank_closed[maybe_open_cmd[16:14]] <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
// if (cmd[22:19] == `DDR_ACTIVATE)
|
|
if (w_this_opening_bank)
|
if (w_this_opening_bank)
|
bank_address[activate_bank_cmd[16:14]]
|
bank_address[activate_bank_cmd[16:14]]
|
<= activate_bank_cmd[13:0];
|
<= activate_bank_cmd[13:0];
|
else if (!w_this_maybe_open)
|
else if (w_this_maybe_open)
|
bank_address[maybe_open_cmd[16:14]]
|
bank_address[maybe_open_cmd[16:14]]
|
<= maybe_open_cmd[13:0];
|
<= maybe_open_cmd[13:0];
|
|
|
|
|
|
//////////
|
//
|
//
|
//
|
//
|
// Okay, let's investigate when we need to do a refresh. Our plan will be to
|
// Data BUS information
|
// do 4 refreshes every tREFI*4 seconds. tREFI = 7.8us, but its a parameter
|
|
// in the number of clocks so that we can handle both 100MHz and 200MHz clocks.
|
|
//
|
|
// Note that 160ns are needed between refresh commands (JEDEC, p172), or
|
|
// 320 clocks @200MHz, or equivalently 160 clocks @100MHz. Thus to issue 4
|
|
// of these refresh cycles will require 4*320=1280 clocks@200 MHz. After this
|
|
// time, no more refreshes will be needed for 6240 clocks.
|
|
//
|
|
// Let's think this through:
|
|
// REFRESH_COST = (n*(320)+24)/(n*1560)
|
|
//
|
|
//
|
//
|
//
|
//
|
reg refresh_ztimer;
|
//////////
|
reg [16:0] refresh_counter;
|
|
reg [2:0] refresh_addr;
|
|
reg [23:0] refresh_instruction;
|
|
always @(posedge i_clk)
|
|
if (reset_override)
|
|
refresh_addr <= 3'hf;
|
|
else if (refresh_ztimer)
|
|
refresh_addr <= refresh_addr + 3'h1;
|
|
else if (refresh_instruction[`DDR_RFBEGIN])
|
|
refresh_addr <= 3'h0;
|
|
|
|
always @(posedge i_clk)
|
|
if (reset_override)
|
|
begin
|
|
refresh_ztimer <= 1'b1;
|
|
refresh_counter <= 17'd0;
|
|
end else if (!refresh_ztimer)
|
|
begin
|
|
refresh_ztimer <= (refresh_counter == 17'h1);
|
|
refresh_counter <= (refresh_counter - 17'h1);
|
|
end else if (refresh_instruction[`DDR_RFTIMER])
|
|
begin
|
|
refresh_ztimer <= 1'b0;
|
|
refresh_counter <= refresh_instruction[16:0];
|
|
end
|
|
|
|
`ifdef QUADRUPLE_REFRESH
|
|
// REFI4 = 13'd6240
|
|
wire [16:0] w_ckREFIn, w_ckREFRst, w_wait_for_idle,
|
|
w_precharge_to_refresh;
|
|
assign w_wait_for_idle = 5+CKCAS;
|
|
assign w_precharge_to_refresh = CKRP-1;
|
|
assign w_ckREFIn[(CKRBITS-1): 0] = CKREFI4-5*CKRFC-2-10;
|
|
assign w_ckREFIn[ 16:(CKRBITS)] = 0;
|
|
assign w_ckREFRst = CKRFC-2-12;
|
|
|
|
always @(posedge i_clk)
|
|
if (refresh_ztimer)
|
|
case(refresh_addr)//NEED-RFC, HAVE-TIMER,
|
|
4'h0: refresh_instruction <= { 3'h2, `DDR_NOOP, w_ckREFIn };
|
|
// 17'd10 = time to complete write, plus write recovery time
|
|
// minus two (cause we can't count zero or one)
|
|
// = WL+4+tWR-2 = 10
|
|
// = 5+4+3-2 = 10
|
|
4'h1: refresh_instruction <= { 3'h6, `DDR_NOOP, w_wait_for_idle };
|
|
4'h2: refresh_instruction <= { 3'h4, `DDR_PRECHARGE, 17'h0400 };
|
|
4'h3: refresh_instruction <= { 3'h6, `DDR_NOOP, w_precharge_to_refresh };
|
|
4'h4: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
|
4'h5: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
|
4'h6: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
|
4'h7: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
|
4'h8: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
|
4'h9: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
|
4'ha: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
|
4'hb: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
|
4'hc: refresh_instruction <= { 3'h2, `DDR_NOOP, w_ckREFRst };
|
|
default:
|
|
refresh_instruction <= { 3'h1, `DDR_NOOP, 17'h00 };
|
|
endcase
|
|
`else
|
|
wire [16:0] w_ckREFI_left, w_ckRFC_nxt, w_wait_for_idle,
|
|
w_precharge_to_refresh;
|
|
assign w_wait_for_idle = 5+CKCAS;
|
|
assign w_precharge_to_refresh = CKRP-2;
|
|
assign w_ckREFI_left[16:0] = { 4'h0, CKREFI }-CKRFC-9
|
|
-w_wait_for_idle
|
|
-w_precharge_to_refresh;
|
|
// assign w_ckREFI_left[16:13] = 0;
|
|
assign w_ckRFC_nxt[8:0] = CKRFC+9'h2;
|
|
assign w_ckRFC_nxt[16:9] = 0;
|
|
|
|
always @(posedge i_clk)
|
|
if (refresh_ztimer)
|
|
case(refresh_addr)//NEED-REFRESH, HAVE-TIMER, BEGIN(start-over)
|
|
3'h0: refresh_instruction <= { 3'h2, `DDR_NOOP, w_ckREFI_left };
|
|
3'h1: refresh_instruction <= { 3'h6, `DDR_NOOP, w_wait_for_idle };
|
|
3'h2: refresh_instruction <= { 3'h4, `DDR_PRECHARGE, 17'h0400 };
|
|
3'h3: refresh_instruction <= { 3'h6, `DDR_NOOP, w_precharge_to_refresh };
|
|
3'h4: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
|
3'h5: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC_nxt };
|
|
default:
|
|
refresh_instruction <= { 3'h1, `DDR_NOOP, 17'h00 };
|
|
endcase
|
|
`endif
|
|
|
|
always @(posedge i_clk)
|
|
if (reset_override)
|
|
refresh_cmd <= { `DDR_NOOP, w_ckREFI_left };
|
|
else if (refresh_ztimer)
|
|
refresh_cmd <= refresh_instruction[20:0];
|
|
always @(posedge i_clk)
|
|
if (reset_override)
|
|
need_refresh <= 1'b0;
|
|
else if (refresh_ztimer)
|
|
need_refresh <= refresh_instruction[`DDR_NEEDREFRESH];
|
|
|
|
|
|
//
|
//
|
//
|
//
|
// Let's track: when will our bus be active? When will we be reading or
|
// Our purpose here is to keep track of when the data bus will be
|
// writing?
|
// active. This is separate from the FIFO which will contain the
|
|
// data to be placed on the bus (when so placed), in that this is
|
|
// a group of shift registers--every position has a location in time,
|
|
// and time always moves forward. The FIFO, on the other hand, only
|
|
// moves forward when data moves onto the bus.
|
//
|
//
|
//
|
//
|
|
|
reg [BUSNOW:0] bus_active, bus_read, bus_new, bus_ack;
|
reg [BUSNOW:0] bus_active, bus_read, bus_new, bus_ack;
|
reg [1:0] bus_subaddr [BUSNOW:0];
|
reg [BUSNOW:0] bus_subaddr, bus_odt;
|
initial bus_active = 0;
|
initial bus_active = 0;
|
initial bus_ack = 0;
|
initial bus_ack = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
bus_active[BUSNOW:0] <= { bus_active[(BUSNOW-1):0], 1'b0 };
|
bus_active[BUSNOW:0] <= { bus_active[(BUSNOW-1):0], 1'b0 };
|
bus_read[BUSNOW:0] <= { bus_read[(BUSNOW-1):0], 1'b0 }; // Drive the d-bus?
|
// Drive the d-bus?
|
|
bus_read[BUSNOW:0] <= { bus_read[(BUSNOW-1):0], 1'b0 };
|
// Is this a new command? i.e., the start of a transaction?
|
// Is this a new command? i.e., the start of a transaction?
|
bus_new[BUSNOW:0] <= { bus_new[(BUSNOW-1):0], 1'b0 };
|
bus_new[BUSNOW:0] <= { bus_new[(BUSNOW-1):0], 1'b0 };
|
|
bus_odt[BUSNOW:0] <= { bus_odt[(BUSNOW-1):0], 1'b0 };
|
// Will this position on the bus get a wishbone acknowledgement?
|
// Will this position on the bus get a wishbone acknowledgement?
|
bus_ack[BUSNOW:0] <= { bus_ack[(BUSNOW-1):0], 1'b0 };
|
bus_ack[BUSNOW:0] <= { bus_ack[(BUSNOW-1):0], 1'b0 };
|
//bus_mask[8:0] <= { bus_mask[7:0], 1'b1 }; // Write this value?
|
//
|
bus_subaddr[8] <= bus_subaddr[7];
|
bus_subaddr[BUSNOW:0] <= { bus_subaddr[(BUSNOW-1):0], 1'b1 };
|
bus_subaddr[7] <= bus_subaddr[6];
|
|
bus_subaddr[6] <= bus_subaddr[5];
|
|
bus_subaddr[5] <= bus_subaddr[4];
|
|
bus_subaddr[4] <= bus_subaddr[3];
|
|
bus_subaddr[3] <= bus_subaddr[2];
|
|
bus_subaddr[2] <= bus_subaddr[1];
|
|
bus_subaddr[1] <= bus_subaddr[0];
|
|
bus_subaddr[0] <= 2'h3;
|
|
|
|
bus_ack[5] <= (bus_ack[4])&&
|
|
((bus_subaddr[5] != bus_subaddr[4])
|
|
||(bus_new[4]));
|
|
if (w_this_rw_move)
|
if (w_this_rw_move)
|
begin
|
begin
|
bus_active[3:0]<= 4'hf; // Once per clock
|
bus_active[1:0]<= 2'h3; // Data transfers in two clocks
|
bus_subaddr[3] <= 2'h0;
|
bus_subaddr[1] <= 1'h0;
|
bus_subaddr[2] <= 2'h1;
|
|
bus_subaddr[1] <= 2'h2;
|
|
bus_new[{ 2'b0, rw_sub }] <= 1'b1;
|
bus_new[{ 2'b0, rw_sub }] <= 1'b1;
|
bus_ack[3:0] <= 4'h0;
|
bus_ack[1:0] <= 2'h0;
|
bus_ack[{ 2'b0, rw_sub }] <= 1'b1;
|
bus_ack[{ 2'b0, rw_sub }] <= 1'b1;
|
|
|
bus_read[3:0] <= (rw_we)? 4'h0:4'hf;
|
bus_read[1:0] <= (rw_we)? 2'h0:2'h3;
|
|
bus_odt[3:0]<= (rw_we)? 4'he:4'h0; // Data transfers in 2 clks
|
end else if ((s_pending)&&(!pipe_stall))
|
end else if ((s_pending)&&(!pipe_stall))
|
begin
|
begin
|
if (bus_subaddr[3] == s_sub)
|
|
bus_ack[4] <= 1'b1;
|
|
if (bus_subaddr[2] == s_sub)
|
|
bus_ack[3] <= 1'b1;
|
|
if (bus_subaddr[1] == s_sub)
|
if (bus_subaddr[1] == s_sub)
|
bus_ack[2] <= 1'b1;
|
bus_ack[2] <= 1'b1;
|
if (bus_subaddr[0] == s_sub)
|
if (bus_subaddr[0] == s_sub)
|
bus_ack[1] <= 1'b1;
|
bus_ack[1] <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
// Need to set o_wb_dqs high one clock prior to any read.
|
// Need to set o_wb_dqs high one clock prior to any read.
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
drive_dqs <= (|bus_active[BUSREG:(BUSREG-1)])
|
begin
|
&&(~(|bus_read[BUSREG:(BUSREG-1)]));
|
drive_dqs[1] <= (bus_active[(BUSREG)])
|
|
&&(!bus_read[(BUSREG)]);
|
|
drive_dqs[0] <= (bus_active[BUSREG:(BUSREG-1)] != 2'b00)
|
|
&&(bus_read[BUSREG:(BUSREG-1)] == 2'b00);
|
|
end
|
|
|
//
|
//
|
//
|
//
|
// Now, let's see, can we issue a read command?
|
// Now, let's see, can we issue a read command?
|
//
|
//
|
| Line 663... |
Line 625... |
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((refresh_ztimer)&&(refresh_instruction[`DDR_NEEDREFRESH]))
|
if ((refresh_ztimer)&&(refresh_instruction[`DDR_NEEDREFRESH]))
|
pre_valid <= 1'b0;
|
pre_valid <= 1'b0;
|
else if (need_refresh)
|
else if (need_refresh)
|
pre_valid <= 1'b0;
|
pre_valid <= 1'b0;
|
else if (w_this_rw_move)
|
|
pre_valid <= 1'b0;
|
|
else if (bus_active[0])
|
|
pre_valid <= 1'b0;
|
|
else
|
else
|
pre_valid <= 1'b1;
|
pre_valid <= 1'b1;
|
|
|
assign w_r_valid = (pre_valid)&&(r_pending)
|
assign w_r_valid = (pre_valid)&&(r_pending)
|
&&(bank_status[r_bank][(CKRP-2)])
|
&&(bank_status[r_bank][(CKRP-2)])
|
| Line 681... |
Line 639... |
&&(bank_address[s_bank]==s_row)
|
&&(bank_address[s_bank]==s_row)
|
&&((s_we)||(bank_wr_ckzro[s_bank]));
|
&&((s_we)||(bank_wr_ckzro[s_bank]));
|
assign w_s_match = (s_pending)&&(r_pending)&&(r_we == s_we)
|
assign w_s_match = (s_pending)&&(r_pending)&&(r_we == s_we)
|
&&(r_row == s_row)&&(r_bank == s_bank)
|
&&(r_row == s_row)&&(r_bank == s_bank)
|
&&(r_col == s_col)
|
&&(r_col == s_col)
|
&&(r_sub > s_sub);
|
&&(r_sub)&&(!s_sub);
|
|
|
reg pipe_stall;
|
reg pipe_stall;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
r_pending <= (i_wb_stb)&&(~o_wb_stall)
|
r_pending <= (i_wb_stb)&&(~o_wb_stall)
|
| Line 695... |
Line 653... |
if (~pipe_stall)
|
if (~pipe_stall)
|
begin
|
begin
|
pipe_stall <= (r_pending)&&(((!w_r_valid)||(valid_bank))&&(!w_s_match));
|
pipe_stall <= (r_pending)&&(((!w_r_valid)||(valid_bank))&&(!w_s_match));
|
o_wb_stall <= (r_pending)&&(((!w_r_valid)||(valid_bank))&&(!w_s_match));
|
o_wb_stall <= (r_pending)&&(((!w_r_valid)||(valid_bank))&&(!w_s_match));
|
end else begin // if (pipe_stall)
|
end else begin // if (pipe_stall)
|
pipe_stall <= (s_pending)&&((!w_s_valid)||(valid_bank)||(r_move)||(last_valid_bank));
|
pipe_stall <= (s_pending)&&((!w_s_valid)||(valid_bank));
|
o_wb_stall <= (s_pending)&&((!w_s_valid)||(valid_bank)||(r_move)||(last_valid_bank));
|
o_wb_stall <= (s_pending)&&((!w_s_valid)||(valid_bank));
|
end
|
end
|
if (need_refresh)
|
if (need_refresh)
|
o_wb_stall <= 1'b1;
|
o_wb_stall <= 1'b1;
|
|
|
if (~pipe_stall)
|
if (~pipe_stall)
|
begin
|
begin
|
r_we <= i_wb_we;
|
r_we <= i_wb_we;
|
r_addr <= i_wb_addr;
|
r_addr <= i_wb_addr;
|
r_data <= i_wb_data;
|
r_data <= i_wb_data;
|
r_row <= i_wb_addr[25:12];
|
r_row <= i_wb_addr[24:11]; // 14 bits row address
|
r_bank <= i_wb_addr[11:9];
|
r_bank <= i_wb_addr[10:8];
|
r_col <= { i_wb_addr[8:2], 3'b000 }; // 9:2
|
r_col <= { i_wb_addr[7:1], 3'b000 }; // 10 bits Caddr
|
r_sub <= i_wb_addr[1:0];
|
r_sub <= i_wb_addr[0]; // Select which 64-bit word
|
|
r_sel <= i_wb_sel;
|
|
|
|
// i_wb_addr[0] is the 8-bit byte selector of 16-bits (ignored)
|
|
// i_wb_addr[1] is the 16-bit half-word selector of 32-bits (ignored)
|
|
// i_wb_addr[2] is the 32-bit word selector of 64-bits (ignored)
|
|
// i_wb_addr[3] is the 64-bit long word selector of 128-bits
|
|
|
// pre-emptive work
|
// pre-emptive work
|
r_nxt_row <= (i_wb_addr[11:9]==3'h7)?i_wb_addr[25:12]+14'h1:i_wb_addr[25:12];
|
r_nxt_row <= (i_wb_addr[10:8]==3'h7)
|
r_nxt_bank <= i_wb_addr[11:9]+3'h1;
|
? (i_wb_addr[24:11]+14'h1)
|
|
: i_wb_addr[24:11];
|
|
r_nxt_bank <= i_wb_addr[10:8]+3'h1;
|
end
|
end
|
|
|
if (~pipe_stall)
|
if (~pipe_stall)
|
begin
|
begin
|
// Moving one down the pipeline
|
// Moving one down the pipeline
|
| Line 726... |
Line 692... |
s_data <= r_data;
|
s_data <= r_data;
|
s_row <= r_row;
|
s_row <= r_row;
|
s_bank <= r_bank;
|
s_bank <= r_bank;
|
s_col <= r_col;
|
s_col <= r_col;
|
s_sub <= r_sub;
|
s_sub <= r_sub;
|
|
s_sel <= (r_we)?(~r_sel):8'h00;
|
|
|
// pre-emptive work
|
// pre-emptive work
|
s_nxt_row <= r_nxt_row;
|
s_nxt_row <= r_nxt_row;
|
s_nxt_bank <= r_nxt_bank;
|
s_nxt_bank <= r_nxt_bank;
|
|
|
// s_match <= w_s_match;
|
|
end
|
end
|
end
|
end
|
|
|
assign w_need_close_this_bank = (r_pending)
|
assign w_need_close_this_bank = (r_pending)
|
&&(bank_open[r_bank])
|
&&(bank_open[r_bank])
|
| Line 777... |
Line 742... |
maybe_open_cmd <= { `DDR_ACTIVATE,r_nxt_bank, r_nxt_row[13:0] };
|
maybe_open_cmd <= { `DDR_ACTIVATE,r_nxt_bank, r_nxt_row[13:0] };
|
|
|
|
|
|
|
valid_bank <= ((w_r_valid)||((pipe_stall)&&(w_s_valid)))
|
valid_bank <= ((w_r_valid)||((pipe_stall)&&(w_s_valid)))
|
&&(!last_valid_bank)&&(!r_move)
|
// &&(!last_valid_bank)&&(!r_move)
|
&&(!w_this_rw_move);
|
&&(!w_this_rw_move);
|
last_valid_bank <= r_move;
|
|
|
|
if ((s_pending)&&(pipe_stall))
|
if ((s_pending)&&(pipe_stall))
|
rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= (s_we)?`DDR_WRITE:`DDR_READ;
|
rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= (s_we)?`DDR_WRITE:`DDR_READ;
|
else if (r_pending)
|
else if (r_pending)
|
rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= (r_we)?`DDR_WRITE:`DDR_READ;
|
rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= (r_we)?`DDR_WRITE:`DDR_READ;
|
| Line 792... |
Line 756... |
if ((s_pending)&&(pipe_stall))
|
if ((s_pending)&&(pipe_stall))
|
rw_cmd[`DDR_WEBIT-1:0] <= { s_bank, 3'h0, 1'b0, s_col };
|
rw_cmd[`DDR_WEBIT-1:0] <= { s_bank, 3'h0, 1'b0, s_col };
|
else
|
else
|
rw_cmd[`DDR_WEBIT-1:0] <= { r_bank, 3'h0, 1'b0, r_col };
|
rw_cmd[`DDR_WEBIT-1:0] <= { r_bank, 3'h0, 1'b0, r_col };
|
if ((s_pending)&&(pipe_stall))
|
if ((s_pending)&&(pipe_stall))
|
rw_sub <= 2'b11 - s_sub;
|
rw_sub <= 1'b1 - s_sub;
|
else
|
else
|
rw_sub <= 2'b11 - r_sub;
|
rw_sub <= 1'b1 - r_sub;
|
if ((s_pending)&&(pipe_stall))
|
if ((s_pending)&&(pipe_stall))
|
rw_we <= s_we;
|
rw_we <= s_we;
|
else
|
else
|
rw_we <= r_we;
|
rw_we <= r_we;
|
|
|
| Line 852... |
Line 816... |
begin
|
begin
|
last_opening_bank <= 1'b0;
|
last_opening_bank <= 1'b0;
|
last_closing_bank <= 1'b0;
|
last_closing_bank <= 1'b0;
|
last_maybe_open <= 1'b0;
|
last_maybe_open <= 1'b0;
|
last_maybe_close <= 1'b0;
|
last_maybe_close <= 1'b0;
|
r_move <= 1'b0;
|
cmd_a <= { `DDR_NOOP, 17'h00 };
|
if (maintenance_override) // Command from either reset or
|
cmd_b <= { `DDR_NOOP, rw_cmd[(`DDR_WEBIT-1):0] };
|
cmd <= maintenance_cmd; // refresh logic
|
|
else if (need_close_bank)
|
if (maintenance_override)
|
|
begin // Command from either reset or refresh logic
|
|
cmd_a <= maintenance_cmd;
|
|
// cmd_b <= { `DDR_NOOP, ...
|
|
end else if (need_close_bank)
|
begin
|
begin
|
cmd <= close_bank_cmd;
|
cmd_a <= close_bank_cmd;
|
|
// cmd_b <= { `DDR_NOOP, ...}
|
last_closing_bank <= 1'b1;
|
last_closing_bank <= 1'b1;
|
end else if (need_open_bank)
|
end else if (need_open_bank)
|
begin
|
begin
|
cmd <= activate_bank_cmd;
|
cmd_a <= activate_bank_cmd;
|
|
// cmd_b <={`DDR_NOOP, ...}
|
last_opening_bank <= 1'b1;
|
last_opening_bank <= 1'b1;
|
end else if (valid_bank)
|
end else if (valid_bank)
|
begin
|
begin
|
cmd <= rw_cmd;
|
cmd_a <= {(rw_cmd[(`DDR_WEBIT)])?`DDR_READ:`DDR_NOOP,
|
r_move <= 1'b1;
|
rw_cmd[(`DDR_WEBIT-1):0] };
|
|
cmd_b <= {(rw_cmd[(`DDR_WEBIT)])?`DDR_NOOP:`DDR_WRITE,
|
|
rw_cmd[(`DDR_WEBIT-1):0] };
|
end else if (maybe_close_next_bank)
|
end else if (maybe_close_next_bank)
|
begin
|
begin
|
cmd <= maybe_close_cmd;
|
cmd_a <= maybe_close_cmd;
|
|
// cmd_b <= {`DDR_NOOP, ... }
|
last_maybe_close <= 1'b1;
|
last_maybe_close <= 1'b1;
|
end else if (maybe_open_next_bank)
|
end else if (maybe_open_next_bank)
|
begin
|
begin
|
cmd <= maybe_open_cmd;
|
cmd_a <= maybe_open_cmd;
|
|
// cmd_b <= {`DDR_NOOP, ... }
|
last_maybe_open <= 1'b1;
|
last_maybe_open <= 1'b1;
|
end else
|
end else
|
cmd <= { `DDR_NOOP, rw_cmd[(`DDR_WEBIT-1):0] };
|
cmd_a <= { `DDR_NOOP, rw_cmd[(`DDR_WEBIT-1):0] };
|
end
|
end
|
|
|
`define LGFIFOLN 4
|
`define LGFIFOLN 4
|
`define FIFOLEN 16
|
`define FIFOLEN 16
|
reg [(`LGFIFOLN-1):0] bus_fifo_head, bus_fifo_tail;
|
reg [(`LGFIFOLN-1):0] bus_fifo_head, bus_fifo_tail;
|
reg [31:0] bus_fifo_data [0:(`FIFOLEN-1)];
|
reg [63:0] bus_fifo_data [0:(`FIFOLEN-1)];
|
reg [1:0] bus_fifo_sub [0:(`FIFOLEN-1)];
|
reg [7:0] bus_fifo_sel [0:(`FIFOLEN-1)];
|
|
reg bus_fifo_sub [0:(`FIFOLEN-1)];
|
reg bus_fifo_new [0:(`FIFOLEN-1)];
|
reg bus_fifo_new [0:(`FIFOLEN-1)];
|
reg pre_ack;
|
reg pre_ack;
|
|
|
// The bus R/W FIFO
|
// The bus R/W FIFO
|
wire w_bus_fifo_read_next_transaction;
|
wire w_bus_fifo_read_next_transaction;
|
assign w_bus_fifo_read_next_transaction = (bus_ack[BUSREG]);
|
assign w_bus_fifo_read_next_transaction = (bus_ack[BUSREG]);
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
pre_ack <= 1'b0;
|
pre_ack <= 1'b0;
|
o_ddr_dm <= 1'b0;
|
|
if (reset_override)
|
if (reset_override)
|
begin
|
begin
|
bus_fifo_head <= {(`LGFIFOLN){1'b0}};
|
bus_fifo_head <= {(`LGFIFOLN){1'b0}};
|
bus_fifo_tail <= {(`LGFIFOLN){1'b0}};
|
bus_fifo_tail <= {(`LGFIFOLN){1'b0}};
|
o_ddr_dm <= 1'b0;
|
|
end else begin
|
end else begin
|
if ((s_pending)&&(!pipe_stall))
|
if ((s_pending)&&(!pipe_stall))
|
bus_fifo_head <= bus_fifo_head + 1'b1;
|
bus_fifo_head <= bus_fifo_head + 1'b1;
|
|
|
o_ddr_dm <= (bus_active[BUSREG])&&(!bus_read[BUSREG]);
|
|
if (w_bus_fifo_read_next_transaction)
|
if (w_bus_fifo_read_next_transaction)
|
begin
|
begin
|
bus_fifo_tail <= bus_fifo_tail + 1'b1;
|
bus_fifo_tail <= bus_fifo_tail + 1'b1;
|
pre_ack <= 1'b1;
|
pre_ack <= 1'b1;
|
o_ddr_dm <= 1'b0;
|
|
end
|
end
|
end
|
end
|
bus_fifo_data[bus_fifo_head] <= s_data;
|
bus_fifo_data[bus_fifo_head] <= s_data;
|
bus_fifo_sub[bus_fifo_head] <= s_sub;
|
bus_fifo_sub[bus_fifo_head] <= s_sub;
|
bus_fifo_new[bus_fifo_head] <= w_this_rw_move;
|
bus_fifo_new[bus_fifo_head] <= w_this_rw_move;
|
|
bus_fifo_sel[bus_fifo_head] <= s_sel;
|
//
|
|
// if ((s_pending)&&(!pipe_stall)&&(!nxt_valid))
|
|
// nxt_fifo_data <= s_data;
|
|
// nxt_fifo_sub <= s_sub;
|
|
// nxt_fifo_new <= w_this_rw_move;
|
|
// nxt_valid <= 1'b1;
|
|
// bus_fifo_head <= bus_fifo_head+1;
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// bus_fifo_tail <= bus_fifo_tail+1;
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// else if (w_bus_fifo_read_next_transaction)
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// nxt_fifo_data <= bus_fifo_data[bus_fifo_tail]
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// nxt_fifo_sub <= bus_fifo_data[bus_fifo_tail]
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// nxt_fifo_new <= bus_fifo_data[bus_fifo_tail]
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// nxt_valid <= (bus_fifo_tail+1 == bus_fifo_head);
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//
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// if ((!valid)||(w_bus_fifo_next_read_transaction))
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// nxt_ <= bus_fifo_x
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end
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end
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|
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assign o_ddr_cs_n = cmd[`DDR_CSBIT];
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assign o_ddr_ras_n = cmd[`DDR_RASBIT];
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assign o_ddr_cas_n = cmd[`DDR_CASBIT];
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assign o_ddr_we_n = cmd[`DDR_WEBIT];
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assign o_ddr_dqs = drive_dqs;
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assign o_ddr_addr = cmd[(`DDR_ADDR_BITS-1):0];
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assign o_ddr_ba = cmd[(`DDR_BABITS+`DDR_ADDR_BITS-1):`DDR_ADDR_BITS];
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_ddr_data <= bus_fifo_data[bus_fifo_tail];
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o_ddr_data <= bus_fifo_data[bus_fifo_tail];
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assign w_precharge_all = (cmd[`DDR_CSBIT:`DDR_WEBIT]==`DDR_PRECHARGE)
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always @(posedge i_clk)
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&&(o_ddr_addr[10]); // 5 bits
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ddr_dm <= (bus_ack[BUSREG])? bus_fifo_sel[bus_fifo_tail]
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: ((!bus_read[BUSREG])? 8'hff: 8'h00);
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always @(posedge i_clk)
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o_ddr_bus_oe <= (bus_active[BUSREG])&&(!bus_read[BUSREG]);
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|
|
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// First, or left, command
|
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assign o_ddr_cmd_a = { cmd_a, drive_dqs[1], ddr_dm[7:4], ddr_odt };
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// Second, or right, command of two
|
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assign o_ddr_cmd_b = { cmd_b, drive_dqs[0], ddr_dm[3:0], ddr_odt };
|
|
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assign o_ddr_bus_oe = drive_dqs; // ~bus_read[BUSNOW];
|
assign w_precharge_all = (cmd_a[`DDR_CSBIT:`DDR_WEBIT]==`DDR_PRECHARGE)
|
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&&(cmd_a[10]);
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|
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// ODT must be in high impedence while reset_n=0, then it can be set
|
// ODT must be in high impedence while reset_n=0, then it can be set
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// to low or high. As per spec, ODT = 0 during reads
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// to low or high. As per spec, ODT = 0 during reads
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_ddr_odt <= (bus_active[BUSREG-3])&&(!bus_read[BUSREG-3])
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ddr_odt <= bus_odt[BUSREG];
|
||(bus_active[BUSREG-4])&&(!bus_read[BUSREG-4])
|
|
||((w_this_rw_move)&&(rw_we)&&(CKCAS<4))
|
|
||(CKCAS>3)&&(bus_active[BUSREG-5])&&(!bus_read[BUSREG-5]);
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|
|
|
always @(posedge i_clk)
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always @(posedge i_clk)
|
o_wb_ack <= pre_ack;
|
o_wb_ack <= pre_ack;
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always @(posedge i_clk)
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always @(posedge i_clk)
|
o_wb_data <= i_ddr_data;
|
o_wb_data <= i_ddr_data;
|
