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Line 93... |
`define MBOOT_READ 5'h06
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`define MBOOT_READ 5'h06
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`define MBOOT_WRITE 5'h0f
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`define MBOOT_WRITE 5'h0f
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`define MBOOT_DESYNC 5'h11
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`define MBOOT_DESYNC 5'h11
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module wbicapetwo(i_clk,
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module wbicapetwo(i_clk,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data);
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o_wb_ack, o_wb_stall, o_wb_data, o_dbg);
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input i_clk;
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input i_clk;
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [4:0] i_wb_addr;
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input [4:0] i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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// Wishbone outputs
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// Wishbone outputs
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output reg o_wb_ack, o_wb_stall;
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output reg o_wb_ack, o_wb_stall;
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output reg [31:0] o_wb_data;
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output reg [31:0] o_wb_data;
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// Debugging output
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output wire [31:0] o_dbg;
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// ICAPE2 interface signals
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// ICAPE2 interface signals
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// These are kept internal to this block ...
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// These are kept internal to this block ...
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reg wb_req, r_we;
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reg wb_req, r_we;
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reg [31:0] r_data;
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reg [31:0] r_data;
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reg [4:0] r_addr;
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reg [4:0] r_addr;
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reg slow_clk;
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`ifdef DIVIDE_BY_FOUR
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reg [1:0] slow_clk_counter;
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reg clk_stb, clk_stall;
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wire slow_clk;
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always @(posedge i_clk)
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begin
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slow_clk <= slow_clk + 2'b01;
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// We'll move on the positive edge of the clock, so therefore
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// clk_stb must be true one clock before that, so we test for
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// it one clock before that.
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clk_stb <= (slow_clk_counter == 2'b10);
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// CLK_STALL is set to true two clocks before any cycle that
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// will, by necessity, stall.
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clk_stall <= (slow_clk_counter != 2'b01);
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end
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assign slow_clk = slow_clk_counter[1];
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`else
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reg slow_clk, clk_stb, clk_stall;
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always @(posedge i_clk)
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begin
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slow_clk <= (slow_clk + 1'b1);
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// We'll move on the positive edge of the clock, so therefore
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// clk_stb must be true one clock before that, so we test for
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// it one clock before that.
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clk_stb <= (slow_clk == 1'b1);
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// CLK_STALL is set to true two clocks before any cycle that
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// will, by necessity, stall.
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clk_stall <= (slow_clk != 1'b0); //True all but one clock
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end
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`endif
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reg [31:0] cfg_in;
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reg [31:0] cfg_in;
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reg cfg_cs_n, cfg_rdwrn;
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reg cfg_cs_n, cfg_rdwrn;
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wire [31:0] cfg_out;
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wire [31:0] cfg_out;
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reg [4:0] state;
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reg [4:0] state;
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initial state = `MBOOT_IDLE;
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initial state = `MBOOT_IDLE;
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initial cfg_cs_n = 1'b1;
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initial cfg_cs_n = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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// In general, o_wb_ack is always zero. The exceptions to this
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// will be handled individually below.
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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// We can simplify our logic a touch by always setting
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// o_wb_data. It will only be examined if o_wb_ack
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// is also true, so this is okay.
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o_wb_data <= cfg_out;
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// Turn any request "off", so that it will not be ack'd, if
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// Turn any request "off", so that it will not be ack'd, if
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// the wb_cyc line is ever lowered.
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// the wb_cyc line is ever lowered.
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wb_req <= wb_req & i_wb_cyc;
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wb_req <= wb_req & i_wb_cyc;
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slow_clk <= slow_clk ^ 1'b1;
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o_wb_stall <= (state != `MBOOT_IDLE)||(clk_stall);
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o_wb_stall <= (state != `MBOOT_IDLE)&&(slow_clk);
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if (clk_stb)
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if (~slow_clk)
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begin
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begin
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state <= state + 5'h01;
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state <= state + 5'h01;
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case(state)
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case(state)
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`MBOOT_IDLE: begin
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`MBOOT_IDLE: begin
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cfg_cs_n <= 1'b1;
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cfg_cs_n <= 1'b1;
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| Line 140... |
Line 179... |
o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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r_addr <= i_wb_addr;
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r_addr <= i_wb_addr;
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r_data <= i_wb_data;
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r_data <= i_wb_data;
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r_we <= i_wb_we;
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r_we <= i_wb_we;
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if(i_wb_stb)
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if(i_wb_stb) // &&(!o_wb_stall)
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begin
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begin
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state <= `MBOOT_START;
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state <= `MBOOT_START;
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wb_req <= 1'b1;
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wb_req <= 1'b1;
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//
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//
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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end end
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end end
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`MBOOT_START: cfg_in <= 32'hffffffff; // NOOP
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`MBOOT_START: begin
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cfg_in <= 32'hffffffff; // NOOP
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cfg_cs_n <= 1'b1;
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end
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5'h02: begin
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5'h02: begin
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cfg_cs_n <= 1'b0; // Activate interface
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cfg_cs_n <= 1'b0; // Activate interface
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cfg_rdwrn <= 1'b0;
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cfg_rdwrn <= 1'b0;
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cfg_in <= 32'h20000000; // NOOP
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cfg_in <= 32'h20000000; // NOOP
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end
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end
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5'h03: cfg_in <= 32'haa995566; // Sync word
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5'h03: begin
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5'h04: cfg_in <= 32'h20000000; // NOOP
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cfg_in <= 32'haa995566; // Sync word
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cfg_cs_n <= 1'b0;
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end
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5'h04: begin
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cfg_in <= 32'h20000000; // NOOP
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cfg_cs_n <= 1'b0;
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end
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5'h05: begin
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5'h05: begin
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cfg_in <= 32'h20000000; // NOOP
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cfg_in <= 32'h20000000; // NOOP
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state <= (r_we) ? `MBOOT_WRITE : `MBOOT_READ;
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state <= (r_we) ? `MBOOT_WRITE : `MBOOT_READ;
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cfg_cs_n <= 1'b0;
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end
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`MBOOT_READ: begin
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cfg_cs_n <= 1'b0;
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cfg_in <= { 8'h28, 6'h0, r_addr, 13'h001 };
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end
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5'h07: begin
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cfg_cs_n <= 1'b0;
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cfg_in <= 32'h20000000; // NOOP
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end
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5'h08: begin
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cfg_cs_n <= 1'b0;
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cfg_in <= 32'h20000000; // NOOP
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end
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end
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`MBOOT_READ: cfg_in <= { 8'h28, 6'h0, r_addr, 13'h001 };
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5'h07: cfg_in <= 32'h20000000; // NOOP
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5'h08: cfg_in <= 32'h20000000; // NOOP
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5'h09: begin // Idle the interface before the read cycle
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5'h09: begin // Idle the interface before the read cycle
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cfg_cs_n <= 1'b1;
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cfg_cs_n <= 1'b1;
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cfg_rdwrn <= 1'b1;
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cfg_rdwrn <= 1'b1;
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cfg_in <= 32'h20000000; // NOOP
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cfg_in <= 32'h20000000; // NOOP
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end
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end
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5'h0a: begin // Re-activate the interface and wait 3 cycles
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5'h0a: begin // Re-activate the interface and wait 3 cycles
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cfg_cs_n <= 1'b0;
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cfg_cs_n <= 1'b0;
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cfg_rdwrn <= 1'b1;
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cfg_rdwrn <= 1'b1;
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cfg_in <= 32'h20000000; // NOOP
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cfg_in <= 32'h20000000; // NOOP
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end
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end
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5'h0b: // ... still waiting, cycle two
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5'h0b: begin // ... still waiting, cycle two
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cfg_in <= 32'h20000000; // NOOP
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cfg_in <= 32'h20000000; // NOOP
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5'h0c: // ... still waiting, cycle three
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cfg_cs_n <= 1'b0;
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end
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5'h0c: begin // ... still waiting, cycle three
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cfg_in <= 32'h20000000; // NOOP
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cfg_in <= 32'h20000000; // NOOP
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5'h0d: // ... still waiting, cycle four
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cfg_cs_n <= 1'b0;
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end
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5'h0d: begin // ... still waiting, cycle four
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cfg_in <= 32'h20000000; // NOOP
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cfg_in <= 32'h20000000; // NOOP
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cfg_cs_n <= 1'b0;
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end
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5'h0e: begin // and now our answer is there
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5'h0e: begin // and now our answer is there
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cfg_cs_n <= 1'b1;
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cfg_cs_n <= 1'b1;
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cfg_rdwrn <= 1'b1;
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cfg_rdwrn <= 1'b1;
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cfg_in <= 32'h20000000; // NOOP
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cfg_in <= 32'h20000000; // NOOP
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//
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//
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// Wishbone return
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// Wishbone return
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o_wb_ack <= wb_req;
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o_wb_ack <= wb_req;
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o_wb_data <= cfg_out;
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// o_wb_data <= cfg_out; // Independent of state
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wb_req <= 1'b0;
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wb_req <= 1'b0;
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//
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//
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state <= `MBOOT_DESYNC;
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state <= `MBOOT_DESYNC;
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end
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end
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`MBOOT_WRITE: // Issue a write command to the given address
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`MBOOT_WRITE: begin
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// Issue a write command to the given address
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cfg_in <= { 8'h30, 6'h0, r_addr, 13'h001 };
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cfg_in <= { 8'h30, 6'h0, r_addr, 13'h001 };
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5'h10: cfg_in <= r_data; // Write the value
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cfg_cs_n <= 1'b0;
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end
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5'h10: begin
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cfg_in <= r_data; // Write the value
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cfg_cs_n <= 1'b0;
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end
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`MBOOT_DESYNC: begin
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`MBOOT_DESYNC: begin
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cfg_cs_n <= 1'b0;
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cfg_cs_n <= 1'b0;
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cfg_rdwrn <= 1'b0;
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cfg_rdwrn <= 1'b0;
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cfg_in <= 32'h20000000; // 1st NOOP
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cfg_in <= 32'h20000000; // 1st NOOP
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end
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end
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5'h12: cfg_in <= 32'h20000000; // 2nd NOOP
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5'h12: begin
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5'h13: cfg_in <= 32'h30008001; // Write to CMD register
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cfg_cs_n <= 1'b0;
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5'h14: cfg_in <= 32'h0000000d; // DESYNC command
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cfg_in <= 32'h20000000; // 2nd NOOP
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5'h15: cfg_in <= 32'h20000000; // NOOP
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end
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5'h16: cfg_in <= 32'h20000000; // NOOP
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5'h13: begin
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cfg_cs_n <= 1'b0;
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cfg_in <= 32'h30008001; // Write to CMD register
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end
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5'h14: begin
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cfg_cs_n <= 1'b0;
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cfg_in <= 32'h0000000d; // DESYNC command
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end
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5'h15: begin
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cfg_cs_n <= 1'b0;
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cfg_in <= 32'h20000000; // NOOP
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end
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5'h16: begin
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cfg_cs_n <= 1'b0;
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cfg_in <= 32'h20000000; // NOOP
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end
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5'h17: begin
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5'h17: begin
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// Acknowledge the bus transaction, it is now complete
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// Acknowledge the bus transaction, it is now complete
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o_wb_ack <= wb_req;
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o_wb_ack <= wb_req;
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wb_req <= 1'b0;
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wb_req <= 1'b0;
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//
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//
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| Line 215... |
Line 300... |
cfg_in <= 32'hffffffff; // DUMMY
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cfg_in <= 32'hffffffff; // DUMMY
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//
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//
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state <= `MBOOT_IDLE;
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state <= `MBOOT_IDLE;
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end
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end
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default: begin
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default: begin
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o_wb_ack <= 1'b0;
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wb_req <= 1'b0;
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cfg_cs_n <= 1'b1;
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cfg_cs_n <= 1'b1;
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cfg_rdwrn <= 1'b0;
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cfg_rdwrn <= 1'b0;
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state <= `MBOOT_IDLE;
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state <= `MBOOT_IDLE;
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cfg_in <= 32'hffffffff; // DUMMY WORD
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cfg_in <= 32'hffffffff; // DUMMY WORD
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end
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end
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endcase
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endcase
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end else begin
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o_wb_ack <= 1'b0;
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end
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end
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end
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end
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genvar k;
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genvar k;
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//
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//
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| Line 257... |
Line 340... |
end endgenerate
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end endgenerate
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ICAPE2 #(.ICAP_WIDTH("X32")) reconfig(.CLK(slow_clk),
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ICAPE2 #(.ICAP_WIDTH("X32")) reconfig(.CLK(slow_clk),
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.CSIB(cfg_cs_n), .RDWRB(cfg_rdwrn),
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.CSIB(cfg_cs_n), .RDWRB(cfg_rdwrn),
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.I(bit_swapped_cfg_in), .O(bit_swapped_cfg_out));
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.I(bit_swapped_cfg_in), .O(bit_swapped_cfg_out));
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assign o_dbg = {
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`ifdef DIVIDE_BY_FOUR
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slow_clk_counter, clk_stb, clk_stall,
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`else
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1'b0, slow_clk, clk_stb, clk_stall,
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`endif
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i_wb_stb, o_wb_ack, cfg_cs_n, cfg_rdwrn,
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o_wb_stall, state, 2'h0,
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cfg_in[7:0],
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cfg_out[7:0] };
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endmodule
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endmodule
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