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Line 94... |
`define MBOOT_WRITE 5'h0f
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`define MBOOT_WRITE 5'h0f
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`define MBOOT_DESYNC 5'h11
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`define MBOOT_DESYNC 5'h11
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module wbicapetwo(i_clk,
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module wbicapetwo(i_clk,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data, o_dbg);
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o_wb_ack, o_wb_stall, o_wb_data, o_dbg);
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parameter LGDIV = 3; /// Log of the clock divide
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input i_clk;
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input i_clk;
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [4:0] i_wb_addr;
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input [4:0] i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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Line 112... |
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reg wb_req, r_we;
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reg wb_req, r_we;
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reg [31:0] r_data;
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reg [31:0] r_data;
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reg [4:0] r_addr;
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reg [4:0] r_addr;
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`ifdef DIVIDE_BY_FOUR
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reg [1:0] slow_clk_counter;
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reg clk_stb, clk_stall;
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reg clk_stb, clk_stall;
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wire slow_clk;
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wire slow_clk;
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generate
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if (LGDIV <= 1)
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begin
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reg r_slow_clk;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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slow_clk <= slow_clk + 2'b01;
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r_slow_clk <= (slow_clk + 1'b1);
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// We'll move on the positive edge of the clock, so therefore
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// We'll move on the positive edge of the clock,
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// clk_stb must be true one clock before that, so we test for
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// so therefore clk_stb must be true one clock before
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// it one clock before that.
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// that, so we test for it one clock before that.
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clk_stb <= (slow_clk_counter == 2'b10);
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clk_stb <= (slow_clk == 1'b1);
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// CLK_STALL is set to true two clocks before any cycle that
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// CLK_STALL is set to true two clocks before any
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// will, by necessity, stall.
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// cycle that will, by necessity, stall.
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clk_stall <= (slow_clk_counter != 2'b01);
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clk_stall <= (slow_clk != 1'b0); //True all but 1ckcycle
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end
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end
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assign slow_clk = slow_clk_counter[1];
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assign slow_clk = r_slow_clk;
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`else
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end else begin
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reg slow_clk, clk_stb, clk_stall;
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reg [(LGDIV-1):0] slow_clk_counter;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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slow_clk <= (slow_clk + 1'b1);
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slow_clk_counter <= slow_clk_counter + 1'b1;
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// We'll move on the positive edge of the clock, so therefore
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// We'll move on the positive edge of the clock, so therefore
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// clk_stb must be true one clock before that, so we test for
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// clk_stb must be true one clock before that, so we test for
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// it one clock before that.
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// it one clock before that.
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clk_stb <= (slow_clk == 1'b1);
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clk_stb <= (slow_clk_counter=={{(LGDIV){1'b1}},1'b0});
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// CLK_STALL is set to true two clocks before any cycle that
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// CLK_STALL is set to true two clocks before any cycle that
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// will, by necessity, stall.
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// will, by necessity, stall.
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clk_stall <= (slow_clk != 1'b0); //True all but one clock
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clk_stall <= (slow_clk_counter!={{(LGDIV){1'b0}},1'b1});
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end
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end
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`endif
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assign slow_clk = slow_clk_counter[(LGDIV-1)];
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end endgenerate
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reg [31:0] cfg_in;
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reg [31:0] cfg_in;
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reg cfg_cs_n, cfg_rdwrn;
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reg cfg_cs_n, cfg_rdwrn;
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wire [31:0] cfg_out;
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wire [31:0] cfg_out;
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reg [4:0] state;
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reg [4:0] state;
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