| Line 317... |
Line 317... |
o_wb_err <= 1'b0;
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o_wb_err <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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end
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end
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end
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end
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//
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// The debug wires are set up for a 6-bit ID. In hind sight,
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// I only ever needed 5-bit ID's. Hence, let's expand those
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// five bit ID's for 6-bits so we can still fit nicely into
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// our 32-bit words.
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//
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wire [5:0] six_head, six_tail, six_rid, six_bid;
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assign six_head = {{(6-LGFIFOLN){1'b0}}, fifo_head };
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assign six_tail = {{(6-LGFIFOLN){1'b0}}, fifo_tail };
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assign six_rid = {{(6-LGFIFOLN){1'b0}}, i_axi_rid };
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assign six_bid = {{(6-LGFIFOLN){1'b0}}, i_axi_bid };
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assign o_dbg = {
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assign o_dbg = {
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i_wb_stb, o_wb_stall, o_wb_ack, o_wb_err,
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i_wb_stb, o_wb_stall, o_wb_ack, o_wb_err,
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fifo_head, fifo_tail, // 12 bits
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six_head, six_tail, // 12 bits
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{ ((i_axi_rvalid)&&(o_axi_rready)) ? i_axi_rid
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{ ((i_axi_rvalid)&&(o_axi_rready)) ? six_rid
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: ((i_axi_bvalid)&&(o_axi_bready)) ? i_axi_bid
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: ((i_axi_bvalid)&&(o_axi_bready)) ? six_bid
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: 6'hf }, // 6 bits
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: 6'hf }, // 6 bits
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o_axi_arvalid, i_axi_arready,
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o_axi_arvalid, i_axi_arready,
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o_axi_awvalid, i_axi_awready,
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o_axi_awvalid, i_axi_awready,
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o_axi_wvalid, i_axi_wready, // 28 bits so far ...
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o_axi_wvalid, i_axi_wready, // 28 bits so far ...
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i_axi_rvalid, i_axi_bvalid, 2'b00
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i_axi_rvalid, i_axi_bvalid, 2'b00
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