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Line 56... |
wire dev_busy;
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wire dev_busy;
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lloled #(CBITS)
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lloled #(CBITS)
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lwlvl(i_clk, dev_wr, dev_dbit, dev_word, dev_len, dev_busy,
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lwlvl(i_clk, dev_wr, dev_dbit, dev_word, dev_len, dev_busy,
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o_sck, o_cs_n, o_mosi, o_dbit);
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o_sck, o_cs_n, o_mosi, o_dbit);
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`define EXTRA_WB_DELAY
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`ifdef EXTRA_WB_DELAY
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reg r_wb_stb, r_wb_we;
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reg [31:0] r_wb_data;
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reg [1:0] r_wb_addr;
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always @(posedge i_clk)
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r_wb_stb <= i_stb;
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always @(posedge i_clk)
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r_wb_we <= i_we;
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always @(posedge i_clk)
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r_wb_data <= i_data;
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always @(posedge i_clk)
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r_wb_addr <= i_addr;
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`else
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wire r_wb_stb, r_wb_we;
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wire r_wb_data;
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wire [1:0] r_wb_addr;
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assign r_wb_stb = i_stb;
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assign r_wb_we = i_we;
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assign r_wb_data = i_data;
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assign r_wb_addr = i_addr;
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`endif
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reg r_busy;
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reg r_busy;
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reg [3:0] r_len;
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reg [3:0] r_len;
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reg [31:0] r_a, r_b;
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reg [31:0] r_a, r_b;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_stb)&&(i_we))
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if ((r_wb_stb)&&(r_wb_we))
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begin
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begin
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if (i_addr[1:0]==2'b01)
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if (r_wb_addr[1:0]==2'b01)
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r_a <= i_data;
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r_a <= r_wb_data;
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if (i_addr[1:0]==2'b10)
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if (r_wb_addr[1:0]==2'b10)
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r_b <= i_data;
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r_b <= r_wb_data;
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end else if (r_cstb)
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end else if (r_cstb)
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begin
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begin
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r_a <= 32'h00;
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r_a <= 32'h00;
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r_b <= 32'h00;
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r_b <= 32'h00;
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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case (i_addr)
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case (r_wb_addr)
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2'b00: o_data <= { 13'h00, o_pwr, 8'h00, r_len, 3'h0, r_busy };
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2'b00: o_data <= { 13'h00, o_pwr, 8'h00, r_len, 3'h0, r_busy };
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2'b01: o_data <= r_a;
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2'b01: o_data <= r_a;
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2'b10: o_data <= r_b;
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2'b10: o_data <= r_b;
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2'b11: o_data <= { 13'h00, o_pwr, 8'h00, r_len, 3'h0, r_busy };
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2'b11: o_data <= { 13'h00, o_pwr, 8'h00, r_len, 3'h0, r_busy };
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endcase
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endcase
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end
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end
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initial o_ack = 1'b0;
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initial o_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_ack <= i_stb;
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o_ack <= r_wb_stb;
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assign o_stall = 1'b0;
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assign o_stall = 1'b0;
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reg r_cstb, r_dstb, r_pstb;
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reg r_cstb, r_dstb, r_pstb;
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reg [23:0] r_data;
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reg [23:0] r_data;
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initial r_cstb = 1'b0;
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initial r_cstb = 1'b0;
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initial r_dstb = 1'b0;
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initial r_dstb = 1'b0;
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initial r_pstb = 1'b0;
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initial r_pstb = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_cstb <= (i_stb)&&(i_addr[1:0]==2'b00);
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r_cstb <= (r_wb_stb)&&(r_wb_addr[1:0]==2'b00);
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_dstb <= (i_stb)&&(i_addr[1:0]==2'b11)&&(i_data[22:20]==3'h0);
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r_dstb <= (r_wb_stb)&&(r_wb_addr[1:0]==2'b11)&&(r_wb_data[22:20]==3'h0);
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_pstb <= (i_stb)&&(i_addr[1:0]==2'b11)&&(i_data[22:20]!=3'h0);
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r_pstb <= (r_wb_stb)&&(r_wb_addr[1:0]==2'b11)&&(r_wb_data[22:20]!=3'h0);
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_data <= i_data[23:0];
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r_data <= r_wb_data[23:0];
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initial o_pwr = 3'h0;
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initial o_pwr = 3'h0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (r_pstb)
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if (r_pstb)
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o_pwr <= ((o_pwr)&(~r_data[22:20]))
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o_pwr <= ((o_pwr)&(~r_data[22:20]))
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|((i_data[18:16])&(r_data[22:20]));
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|((r_wb_data[18:16])&(r_data[22:20]));
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reg [3:0] b_len;
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reg [3:0] b_len;
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always @(posedge i_clk)
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always @(posedge i_clk)
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casez(i_data[31:28])
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casez(r_wb_data[31:28])
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4'b000?: b_len <= (i_data[16])? 4'h1:4'h2;
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4'b000?: b_len <= (r_wb_data[16])? 4'h1:4'h2;
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4'b0010: b_len <= 4'h3;
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4'b0010: b_len <= 4'h3;
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4'b0011: b_len <= 4'h4;
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4'b0011: b_len <= 4'h4;
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4'b0100: b_len <= 4'h5;
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4'b0100: b_len <= 4'h5;
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4'b0101: b_len <= 4'h6;
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4'b0101: b_len <= 4'h6;
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4'b0110: b_len <= 4'h7;
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4'b0110: b_len <= 4'h7;
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