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[/] [openarty/] [trunk/] [rtl/] [wbscopc.v] - Diff between revs 3 and 30

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///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    wbscopc.v
// Filename:    wbscopc.v
//
//
// Project:     FPGA Library of Routines
// Project:     FPGA Library of Routines
//
//
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//      are valuable, but could never be done if the scope wasn't compressed.
//      are valuable, but could never be done if the scope wasn't compressed.
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
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//
//
// License:     GPL, v3, as defined and found on www.gnu.org,
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
/////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
//
//
module wbscopc(i_clk, i_ce, i_trigger, i_data,
module wbscopc(i_clk, i_ce, i_trigger, i_data,
        i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
        i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
        o_wb_ack, o_wb_stall, o_wb_data,
        o_wb_ack, o_wb_stall, o_wb_data,

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