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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbscope.v
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// Filename: wbscope.v
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//
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//
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// Project: FPGA Library of Routines
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// Project: FPGA Library of Routines
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//
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//
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// dw_ A wire/net, controlled by the data clock
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// dw_ A wire/net, controlled by the data clock
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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/////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module wbscope(i_clk, i_ce, i_trigger, i_data,
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module wbscope(i_clk, i_ce, i_trigger, i_data,
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i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_interrupt);
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o_interrupt);
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parameter LGMEM = 5'd10, BUSW = 32, SYNCHRONOUS=1;
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parameter LGMEM = 5'd10, BUSW = 32, SYNCHRONOUS=1,
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DEFAULT_HOLDOFF = ((1<<(LGMEM-1))-4);
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// The input signals that we wish to record
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// The input signals that we wish to record
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input i_clk, i_ce, i_trigger;
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input i_clk, i_ce, i_trigger;
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input [(BUSW-1):0] i_data;
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input [(BUSW-1):0] i_data;
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// The WISHBONE bus for reading and configuring this scope
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// The WISHBONE bus for reading and configuring this scope
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input i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
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// Our status/config register
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// Our status/config register
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wire bw_reset_request, bw_manual_trigger,
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wire bw_reset_request, bw_manual_trigger,
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bw_disable_trigger, bw_reset_complete;
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bw_disable_trigger, bw_reset_complete;
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reg [22:0] br_config;
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reg [22:0] br_config;
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wire [19:0] bw_holdoff;
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wire [19:0] bw_holdoff;
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initial br_config = ((1<<(LGMEM-1))-4);
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initial br_config = DEFAULT_HOLDOFF;
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_addr))
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if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_addr))
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begin
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begin
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if (i_wb_we)
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if (i_wb_we)
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br_config <= { i_wb_data[31],
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br_config <= { i_wb_data[31],
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assign dw_manual_trigger = bw_manual_trigger;
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assign dw_manual_trigger = bw_manual_trigger;
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assign dw_disable_trigger = bw_disable_trigger;
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assign dw_disable_trigger = bw_disable_trigger;
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assign bw_reset_complete = bw_reset_request;
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assign bw_reset_complete = bw_reset_request;
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end else begin
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end else begin
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reg r_reset_complete;
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reg r_reset_complete;
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reg [2:0] r_iflags, q_iflags;
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(* ASYNC_REG = "TRUE" *) reg [2:0] q_iflags;
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reg [2:0] r_iflags;
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// Resets are synchronous to the bus clock, not the data clock
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// Resets are synchronous to the bus clock, not the data clock
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// so do a clock transfer here
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// so do a clock transfer here
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initial q_iflags = 3'b000;
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initial q_iflags = 3'b000;
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initial r_reset_complete = 1'b0;
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initial r_reset_complete = 1'b0;
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assign dw_reset = r_iflags[2];
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assign dw_reset = r_iflags[2];
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assign dw_manual_trigger = r_iflags[1];
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assign dw_manual_trigger = r_iflags[1];
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assign dw_disable_trigger = r_iflags[0];
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assign dw_disable_trigger = r_iflags[0];
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reg q_reset_complete, qq_reset_complete;
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(* ASYNC_REG = "TRUE" *) reg q_reset_complete;
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reg qq_reset_complete;
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// Pass an acknowledgement back from the data clock to the bus
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// Pass an acknowledgement back from the data clock to the bus
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// clock that the reset has been accomplished
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// clock that the reset has been accomplished
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initial q_reset_complete = 1'b0;
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initial q_reset_complete = 1'b0;
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initial qq_reset_complete = 1'b0;
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initial qq_reset_complete = 1'b0;
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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//
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//
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// Determine when memory is full and capture is complete
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// Determine when memory is full and capture is complete
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//
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//
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// Writes take place on the data clock
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// Writes take place on the data clock
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reg dr_stopped;
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reg dr_stopped;
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reg [19:0] counter; // This is unsigned
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(* ASYNC_REG="TRUE" *) reg [19:0] counter;// This is unsigned
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initial dr_stopped = 1'b0;
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initial dr_stopped = 1'b0;
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initial counter = 20'h0000;
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initial counter = 20'h0000;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (dw_reset)
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if (dw_reset)
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begin
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begin
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// These aren't a problem, since none of these are strobe
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// These aren't a problem, since none of these are strobe
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// signals. They goes from low to high, and then stays high
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// signals. They goes from low to high, and then stays high
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// for many clocks. Swapping is thus easy--two flip flops to
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// for many clocks. Swapping is thus easy--two flip flops to
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// protect against meta-stability and we're done.
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// protect against meta-stability and we're done.
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//
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//
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reg [2:0] q_oflags, r_oflags;
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(* ASYNC_REG = "TRUE" *) reg [2:0] q_oflags;
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reg [2:0] r_oflags;
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initial q_oflags = 3'h0;
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initial q_oflags = 3'h0;
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initial r_oflags = 3'h0;
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initial r_oflags = 3'h0;
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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if (bw_reset_request)
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if (bw_reset_request)
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begin
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begin
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