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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbureadcw.v
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// Filename: wbureadcw.v
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//
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//
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// Project: FPGA library
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// Project: FPGA library
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//
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//
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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// Goal: single clock pipeline, 50 slices or less
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// Goal: single clock pipeline, 50 slices or less
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//
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//
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module wbureadcw(i_clk, i_stb, i_valid, i_hexbits,
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module wbureadcw(i_clk, i_stb, i_valid, i_hexbits,
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