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[/] [openarty/] [trunk/] [rtl/] [xioddr.v] - Diff between revs 3 and 13

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// Filename:    xioddr.v
// Filename:    xioddr.v
//
//
// Project:     OpenArty, an entirely open SoC based upon the Arty platform
// Project:     OpenArty, an entirely open SoC based upon the Arty platform
//
//
// Purpose:     For the DDR3 SDRAM, this handles the Xilinx specific portions
// Purpose:     For the DDR3 SDRAM, this handles the Xilinx specific portions
//              of the IO necessary to make this happen for one pin only.
//              of the IO necessary to make this happen for one pin only.  (In
 
//      the end, this never worked for the DDR3 SDRAM ...)  In the case of the
 
//      QSPI flash, this module helps to reduce the logic delays on the "high
 
//      speed" flash data wires (it's not really used in any DDR mode in that
 
//      case ...).
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
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//
//
//
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
//
//
module  xioddr(i_clk, i_oe, i_v, o_v, io_w);
module  xioddr(i_clk, i_oe, i_v, o_v, io_pin);
        input   i_clk, i_oe;
        input   i_clk, i_oe;
        input   [1:0]    i_v;
        input   [1:0]    i_v;
        output  [1:0]    o_v;
        output  [1:0]    o_v;
        inout           io_w;
        inout           io_pin;
 
 
        wire    w_internal;
        wire    w_internal;
 
        reg     last;
 
        always @(posedge i_clk)
 
                last <= i_v[1];
 
 
        ODDR #(
        ODDR #(
                .DDR_CLK_EDGE("OPPOSITE_EDGE"),
                .DDR_CLK_EDGE("SAME_EDGE"),
                .INIT(1'b0),
                .INIT(1'b0),
                .SRTYPE("SYNC")
                .SRTYPE("SYNC")
        ) ODDRi(
        ) ODDRi(
                .Q(w_internal),
                .Q(w_internal),
                .C(i_clk),
                .C(i_clk),
                .CE(1'b1),
                .CE(1'b1),
                .D1(i_v[0]),
                .D1(last),      // Negative clock edge
                .D2(i_v[1]),
                .D2(i_v[0]),     // Positive clock edge
                .R(1'b0),
                .R(1'b0),
                .S(1'b0));
                .S(1'b0));
 
 
        IDDR #(
        IDDR #(
                .DDR_CLK_EDGE("OPPOSITE_EDGE"),
                .DDR_CLK_EDGE("SAME_EDGE_PIPELINED"),
                .INIT_Q1(1'b0),
                .INIT_Q1(1'b0),
                .INIT_Q2(1'b0),
                .INIT_Q2(1'b0),
                .SRTYPE("SYNC")
                .SRTYPE("SYNC")
        ) IDDRi(
        ) IDDRi(
                .Q1(o_v[0]),
                .Q1(o_v[0]),
                .Q2(o_v[1]),
                .Q2(o_v[1]),
                .C(i_clk),
                .C(i_clk),
                .CE(1'b1),
                .CE(1'b1),
                .D(io_w),
                .D(io_pin),
                .R(1'b0),
                .R(1'b0),
                .S(1'b0));
                .S(1'b0));
 
 
        assign  io_w = (i_oe) ? w_internal:1'bz;
        assign  io_pin = (i_oe) ? w_internal:1'bz;
 
 
endmodule
endmodule
 
 
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