| Line 55... |
Line 55... |
#define R_UARTRX 0x0000010e
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#define R_UARTRX 0x0000010e
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#define R_UARTTX 0x0000010f
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#define R_UARTTX 0x0000010f
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#define R_GPSRX 0x00000110
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#define R_GPSRX 0x00000110
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#define R_GPSTX 0x00000111
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#define R_GPSTX 0x00000111
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// WB Scope registers
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// WB Scope registers
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#define R_QSCOPE 0x00000120 // Quad SPI scope ctrl
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#define R_QSCOPE 0x00000120 // Scope #0: Quad SPI scope ctrl
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#define R_QSCOPED 0x00000121 // and data
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#define R_QSCOPED 0x00000121 // and data
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#define R_GPSCOPE 0x00000122 // GPS configuration scope control
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#define R_CPUSCOPE 0x00000120 // CPU scope (if so configured)
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#define R_CPUSCOPED 0x00000121 // and data
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#define R_GPSCOPE 0x00000122 // Scope #1: GPS config scope control
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#define R_GPSCOPED 0x00000123 // and data
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#define R_GPSCOPED 0x00000123 // and data
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#define R_CFGSCOPE 0x00000122 // ICAPE2 configuration scop control
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#define R_CFGSCOPE 0x00000122 // ICAPE2 configuration scop control
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#define R_CFGSCOPED 0x00000123 // and data
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#define R_CFGSCOPED 0x00000123 // and data
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#define R_RAMSCOPE 0x00000124 // DDR3 SDRAM Scope
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#define R_BUSSCOPE 0x00000122 // WBUBUS scope control
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#define R_BUSSCOPED 0x00000123 // and data
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#define R_RAMSCOPE 0x00000124 // Scope #2: DDR3 SDRAM Scope
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#define R_RAMSCOPED 0x00000125 //
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#define R_RAMSCOPED 0x00000125 //
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#define R_NETSCOPE 0x00000126 // Ethernet debug scope
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#define R_NETSCOPE 0x00000126 // Scope #3: Ethernet debug scope
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#define R_NETSCOPED 0x00000127 //
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#define R_NETSCOPED 0x00000127 //
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// RTC Clock Registers
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// RTC Clock Registers
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#define R_CLOCK 0x00000128
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#define R_CLOCK 0x00000128
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#define R_TIMER 0x00000129
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#define R_TIMER 0x00000129
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#define R_STOPWATCH 0x0000012a
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#define R_STOPWATCH 0x0000012a
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Line 84... |
// GPS Loop control, 0x0130
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// GPS Loop control, 0x0130
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#define R_GPS_ALPHA 0x00000130
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#define R_GPS_ALPHA 0x00000130
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#define R_GPS_BETA 0x00000131
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#define R_GPS_BETA 0x00000131
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#define R_GPS_GAMMA 0x00000132
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#define R_GPS_GAMMA 0x00000132
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#define R_GPS_STEP 0x00000133
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#define R_GPS_STEP 0x00000133
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// Network packet interface, 0x0134
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// OLED
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// OLED
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#define R_OLED_CMD 0x00000138
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#define R_OLED_CMD 0x00000134
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#define R_OLED_CDATA 0x00000139
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#define R_OLED_CDATA 0x00000135
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#define R_OLED_CDATB 0x0000013a
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#define R_OLED_CDATB 0x00000136
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#define R_OLED_DATA 0x0000013b
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#define R_OLED_DATA 0x00000137
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// Network packet interface, 0x0184
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#define R_NET_RXCMD 0x00000138
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#define R_NET_TXCMD 0x00000139
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#define R_NET_MACHI 0x0000013a
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#define R_NET_MACLO 0x0000013b
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#define R_NET_RXMISS 0x0000013c
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#define R_NET_RXERR 0x0000013d
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#define R_NET_RXCRC 0x0000013e
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#define R_NET_TXCOL 0x0000013f
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// Unused: 0x13c-0x13f
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// Unused: 0x13c-0x13f
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// GPS Testbench: 0x140-0x147
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// GPS Testbench: 0x140-0x147
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#define R_GPSTB_FREQ 0x00000140
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#define R_GPSTB_FREQ 0x00000140
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#define R_GPSTB_JUMP 0x00000141
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#define R_GPSTB_JUMP 0x00000141
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#define R_GPSTB_ERRHI 0x00000142
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#define R_GPSTB_ERRHI 0x00000142
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| Line 156... |
Line 168... |
#define R_CFG_WBSTAR 0x000001f0
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#define R_CFG_WBSTAR 0x000001f0
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#define R_CFG_TIMER 0x000001f1
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#define R_CFG_TIMER 0x000001f1
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#define R_CFG_BOOTSTS 0x000001f6
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#define R_CFG_BOOTSTS 0x000001f6
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#define R_CFG_CTL1 0x000001f8
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#define R_CFG_CTL1 0x000001f8
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#define R_CFG_BSPI 0x000001ff
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#define R_CFG_BSPI 0x000001ff
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// Network buffer space
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#define R_NET_RXBUF 0x00000800
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#define R_NET_TXBUF 0x00000c00
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// Block RAM memory space
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// Block RAM memory space
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#define MEMBASE 0x00008000
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#define MEMBASE 0x00008000
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#define MEMWORDS 0x00008000
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#define MEMWORDS 0x00008000
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// Flash memory space
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// Flash memory space
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#define EQSPIFLASH 0x00400000
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#define EQSPIFLASH 0x00400000
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#define RESET_ADDRESS 0x004e0000
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#define FLASHWORDS (1<<22)
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#define FLASHWORDS (1<<22)
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// DDR3 SDRAM memory space
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// DDR3 SDRAM memory space
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#define RAMBASE 0x04000000
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#define RAMBASE 0x04000000
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#define SDRAMBASE RAMBASE
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#define SDRAMBASE RAMBASE
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#define RAMWORDS (1<<26)
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#define RAMWORDS (1<<26)
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// Zip CPU Control and Debug registers
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// Zip CPU Control and Debug registers
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#define R_ZIPCTRL 0x01000000
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#define R_ZIPCTRL 0x08000000
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#define R_ZIPDATA 0x01000001
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#define R_ZIPDATA 0x08000001
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// Interrupt control constants
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// Interrupt control constants
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#define GIE 0x80000000 // Enable all interrupts
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#define GIE 0x80000000 // Enable all interrupts
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#define ISPIF_EN 0x82000200 // Enable all, enable QSPI, clear QSPI
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#define ISPIF_EN 0x82000200 // Enable all, enable QSPI, clear QSPI
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#define ISPIF_DIS 0x02000200 // Disable all, disable QSPI
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#define ISPIF_DIS 0x02000200 // Disable all, disable QSPI
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| Line 201... |
Line 217... |
#define CPU_INT 0x0080
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#define CPU_INT 0x0080
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#define CPU_STEP 0x0100
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#define CPU_STEP 0x0100
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#define CPU_STALL 0x0200
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#define CPU_STALL 0x0200
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#define CPU_HALT 0x0400
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#define CPU_HALT 0x0400
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#define CPU_CLRCACHE 0x0800
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#define CPU_CLRCACHE 0x0800
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#define CPU_sR0 (0x0000|CPU_HALT)
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#define CPU_sR0 0x0000
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#define CPU_sSP (0x000d|CPU_HALT)
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#define CPU_sSP 0x000d
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#define CPU_sCC (0x000e|CPU_HALT)
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#define CPU_sCC 0x000e
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#define CPU_sPC (0x000f|CPU_HALT)
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#define CPU_sPC 0x000f
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#define CPU_uR0 (0x0010|CPU_HALT)
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#define CPU_uR0 0x0010
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#define CPU_uSP (0x001d|CPU_HALT)
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#define CPU_uSP 0x001d
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#define CPU_uCC (0x001e|CPU_HALT)
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#define CPU_uCC 0x001e
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#define CPU_uPC (0x001f|CPU_HALT)
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#define CPU_uPC 0x001f
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#define SCOPE_NO_RESET 0x80000000
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#define SCOPE_NO_RESET 0x80000000
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#define SCOPE_TRIGGER (0x08000000|SCOPE_NO_RESET)
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#define SCOPE_TRIGGER (0x08000000|SCOPE_NO_RESET)
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#define SCOPE_MANUAL SCOPE_TRIGGER
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#define SCOPE_DISABLE (0x04000000)
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#define SCOPE_DISABLE (0x04000000)
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typedef struct {
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typedef struct {
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unsigned m_addr;
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unsigned m_addr;
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const char *m_name;
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const char *m_name;
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