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Line 59... |
// WB Scope registers
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// WB Scope registers
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#define R_QSCOPE 0x00000120 // Quad SPI scope ctrl
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#define R_QSCOPE 0x00000120 // Quad SPI scope ctrl
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#define R_QSCOPED 0x00000121 // and data
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#define R_QSCOPED 0x00000121 // and data
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#define R_GPSCOPE 0x00000122 // GPS configuration scope control
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#define R_GPSCOPE 0x00000122 // GPS configuration scope control
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#define R_GPSCOPED 0x00000123 // and data, uses Mouse scope addrs
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#define R_GPSCOPED 0x00000123 // and data, uses Mouse scope addrs
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#define R_ENSCOPE 0x00000124 // Next generation UART-WISHBONE
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#define R_RAMSCOPE 0x00000124 // DDR3 SDRAM Scope
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#define R_ENSCOPED 0x00000125 // conversion scope
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#define R_RAMSCOPED 0x00000125 //
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#define R_RAMSCOPE 0x00000126 // DDR3 SDRAM Scope
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#define R_NETSCOPE 0x00000126 // Ethernet debug scope
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#define R_RAMSCOPED 0x00000127 //
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#define R_NETSCOPED 0x00000127 //
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// RTC Clock Registers
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// RTC Clock Registers
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#define R_CLOCK 0x00000128
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#define R_CLOCK 0x00000128
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#define R_TIMER 0x00000129
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#define R_TIMER 0x00000129
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#define R_STOPWATCH 0x0000012a
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#define R_STOPWATCH 0x0000012a
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#define R_CKALARM 0x0000012b
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#define R_CKALARM 0x0000012b
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Line 162... |
// Flash memory space
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// Flash memory space
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#define EQSPIFLASH 0x00400000
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#define EQSPIFLASH 0x00400000
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#define FLASHWORDS (1<<22)
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#define FLASHWORDS (1<<22)
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// DDR3 SDRAM memory space
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// DDR3 SDRAM memory space
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#define RAMBASE 0x04000000
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#define RAMBASE 0x04000000
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#define SDRAMBASE RAMBASE
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#define RAMWORDS (1<<26)
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#define RAMWORDS (1<<26)
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// Zip CPU Control and Debug registers
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// Zip CPU Control and Debug registers
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#define R_ZIPCTRL 0x01000000
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#define R_ZIPCTRL 0x01000000
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#define R_ZIPDATA 0x01000001
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#define R_ZIPDATA 0x01000001
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