| Line 348... |
Line 348... |
"\t-r\tStart the ZipCPU running from the address in the program file\n");
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"\t-r\tStart the ZipCPU running from the address in the program file\n");
|
}
|
}
|
|
|
int main(int argc, char **argv) {
|
int main(int argc, char **argv) {
|
int skp=0;
|
int skp=0;
|
bool start_when_finished = false;
|
bool start_when_finished = false, verbose = false;
|
unsigned entry = 0;
|
unsigned entry = 0;
|
FLASHDRVR *flash = NULL;
|
FLASHDRVR *flash = NULL;
|
const char *bitfile = NULL, *altbitfile = NULL;
|
const char *bitfile = NULL, *altbitfile = NULL;
|
|
|
if (argc < 2) {
|
if (argc < 2) {
|
| Line 369... |
Line 369... |
exit(EXIT_SUCCESS);
|
exit(EXIT_SUCCESS);
|
break;
|
break;
|
case 'r':
|
case 'r':
|
start_when_finished = true;
|
start_when_finished = true;
|
break;
|
break;
|
|
case 'v':
|
|
verbose = true;
|
|
break;
|
default:
|
default:
|
fprintf(stderr, "Unknown option, -%c\n\n",
|
fprintf(stderr, "Unknown option, -%c\n\n",
|
argv[argn+skp][0]);
|
argv[argn+skp][0]);
|
usage();
|
usage();
|
exit(EXIT_FAILURE);
|
exit(EXIT_FAILURE);
|
| Line 475... |
Line 478... |
&&(secp->m_start+secp->m_len
|
&&(secp->m_start+secp->m_len
|
<= RAMBASE+RAMWORDS))
|
<= RAMBASE+RAMWORDS))
|
||((secp->m_start >= MEMBASE)
|
||((secp->m_start >= MEMBASE)
|
&&(secp->m_start+secp->m_len
|
&&(secp->m_start+secp->m_len
|
<= MEMBASE+MEMWORDS)) ) {
|
<= MEMBASE+MEMWORDS)) ) {
|
for(int i=0; (unsigned)i<secp->m_len; i++) {
|
if (verbose)
|
m_fpga->writei(secp->m_start,
|
printf("Writing to MEM: %08x-%08x\n",
|
secp->m_len,
|
secp->m_start,
|
|
secp->m_start+secp->m_len);
|
|
m_fpga->writei(secp->m_start, secp->m_len,
|
secp->m_data);
|
secp->m_data);
|
}
|
|
} else {
|
} else {
|
if (secp->m_start < startaddr) {
|
if (secp->m_start < startaddr) {
|
codelen += (startaddr-secp->m_start);
|
codelen += (startaddr-secp->m_start);
|
startaddr = secp->m_start;
|
startaddr = secp->m_start;
|
} if (secp->m_start+secp->m_len > startaddr+codelen) {
|
} if (secp->m_start+secp->m_len > startaddr+codelen) {
|
codelen = secp->m_start+secp->m_len-startaddr;
|
codelen = secp->m_start+secp->m_len-startaddr;
|
} memcpy(&fbuf[secp->m_start-EQSPIFLASH],
|
} if (verbose)
|
|
printf("Sending to flash: %08x-%08x\n",
|
|
secp->m_start,
|
|
secp->m_start+secp->m_len);
|
|
memcpy(&fbuf[secp->m_start-EQSPIFLASH],
|
secp->m_data,
|
secp->m_data,
|
secp->m_len*sizeof(FPGA::BUSW));
|
secp->m_len*sizeof(FPGA::BUSW));
|
}
|
}
|
}
|
}
|
if ((flash)&&(!flash->write(startaddr, codelen, &fbuf[startaddr-EQSPIFLASH], true))) {
|
|
|
if ((flash)&&(codelen>0)&&(!flash->write(startaddr, codelen, &fbuf[startaddr-EQSPIFLASH], true))) {
|
fprintf(stderr, "ERR: Could not write program to flash\n");
|
fprintf(stderr, "ERR: Could not write program to flash\n");
|
exit(EXIT_FAILURE);
|
exit(EXIT_FAILURE);
|
} else if (!flash)
|
} else if ((!flash)&&(codelen > 0)) {
|
printf("flash->write(%08x, %d, ... );\n", startaddr,
|
fprintf(stderr, "ERR: Cannot write to flash: Driver didn\'t load\n");
|
codelen);
|
// fprintf(stderr, "flash->write(%08x, %d, ... );\n", startaddr,
|
|
// codelen);
|
|
}
|
if (m_fpga) m_fpga->readio(R_VERSION); // Check for bus errors
|
if (m_fpga) m_fpga->readio(R_VERSION); // Check for bus errors
|
|
|
// Now ... how shall we start this CPU?
|
// Now ... how shall we start this CPU?
|
if (start_when_finished) {
|
if (start_when_finished) {
|
printf("Clearing the CPUs registers\n");
|
printf("Clearing the CPUs registers\n");
|
for(int i=0; i<32; i++) {
|
for(int i=0; i<32; i++) {
|
m_fpga->writeio(R_ZIPCTRL, CPU_HALT|i);
|
m_fpga->writeio(R_ZIPCTRL, CPU_HALT|i);
|
if (i == CPU_sPC)
|
|
m_fpga->writeio(R_ZIPDATA, entry);
|
|
else
|
|
m_fpga->writeio(R_ZIPDATA, 0);
|
m_fpga->writeio(R_ZIPDATA, 0);
|
}
|
}
|
|
|
|
m_fpga->writeio(R_ZIPCTRL, CPU_HALT|CPU_CLRCACHE);
|
|
printf("Setting PC to %08x\n", entry);
|
|
m_fpga->writeio(R_ZIPCTRL, CPU_HALT|CPU_sPC);
|
|
m_fpga->writeio(R_ZIPDATA, entry);
|
|
|
m_fpga->writeio(R_CPUSCOPE, 25);
|
m_fpga->writeio(R_CPUSCOPE, 25);
|
printf("Starting the CPU\n");
|
printf("Starting the CPU\n");
|
m_fpga->writeio(R_ZIPCTRL, CPU_HALT|CPU_CLRCACHE|CPU_RESET);
|
|
m_fpga->writeio(R_ZIPCTRL, CPU_GO|CPU_sPC);
|
m_fpga->writeio(R_ZIPCTRL, CPU_GO|CPU_sPC);
|
} else {
|
} else {
|
printf("The CPU should be fully loaded, you may now\n");
|
printf("The CPU should be fully loaded, you may now\n");
|
printf("start it (from reset/reboot) with:\n");
|
printf("start it (from reset/reboot) with:\n");
|
printf("> wbregs cpu 0x40\n");
|
printf("> wbregs cpu 0x40\n");
|
