| Line 21... |
Line 21... |
Port ( reset : in STD_LOGIC;
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Port ( reset : in STD_LOGIC;
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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FlagsDp : in STD_LOGIC_VECTOR (n downto 0);
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FlagsDp : in STD_LOGIC_VECTOR (n downto 0);
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DataDp : in STD_LOGIC_VECTOR (n downto 0);
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DataDp : in STD_LOGIC_VECTOR (n downto 0);
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MuxDp : out STD_LOGIC_VECTOR (2 downto 0);
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MuxDp : out STD_LOGIC_VECTOR (2 downto 0);
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MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
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ImmDp : out STD_LOGIC_VECTOR (n downto 0);
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ImmDp : out STD_LOGIC_VECTOR (n downto 0);
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DpRegFileWriteAddr : out STD_LOGIC;
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DpAluOp : out aluOps; --! Alu operations
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DpRegFileWriteAddr : out generalRegisters;
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DpRegFileWriteEn : out STD_LOGIC;
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DpRegFileWriteEn : out STD_LOGIC;
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DpRegFileReadAddrA : out STD_LOGIC;
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DpRegFileReadAddrA : out generalRegisters;
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DpRegFileReadAddrB : out STD_LOGIC;
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DpRegFileReadAddrB : out generalRegisters;
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DpRegFileReadEnA : out STD_LOGIC;
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DpRegFileReadEnA : out STD_LOGIC;
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DpRegFileReadEnB : out STD_LOGIC;
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DpRegFileReadEnB : out STD_LOGIC;
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MemoryDataRead : out std_logic;
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MemoryDataRead : out std_logic;
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MemoryDataWrite : out std_logic;
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MemoryDataWrite : out std_logic;
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MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0);
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MemoryDataInput : in STD_LOGIC_VECTOR (n downto 0);
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| Line 64... |
Line 66... |
end process;
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end process;
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-- Next state logic (Execution states)
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-- Next state logic (Execution states)
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process (clk, currentCpuState)
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process (clk, currentCpuState)
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begin
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begin
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if (currentCpuState /= execute) and (currentCpuState /= executing) then
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if ( (currentCpuState /= execute) and (currentCpuState /= executing) ) then
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currentExState <= s0;
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currentExState <= initInstructionExecution;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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currentExState <= nextExState;
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currentExState <= nextExState;
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end if;
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end if;
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end process;
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end process;
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|
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| Line 105... |
Line 107... |
MemoryDataRead <= '0';
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MemoryDataRead <= '0';
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MemoryDataWrite <= '0';
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MemoryDataWrite <= '0';
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|
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-- The high attribute points to the highes bit position
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-- The high attribute points to the highes bit position
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case opcodeIR is
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case opcodeIR is
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when mov_reg =>
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when mov_reg | mov_val | add_reg | sub_reg | and_reg | or_reg | xor_reg =>
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nextCpuState <= execute;
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nextCpuState <= execute;
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cyclesExecute := 2;
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cyclesExecute := 3; -- Wait 3 cycles for mov operation
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currInstruction <= IR;
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currInstruction <= IR;
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-- Invalid instruction (Now will be ignored, but latter should raise a trap
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-- Invalid instruction (Now will be ignored, but latter should raise a trap
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when others =>
|
when others =>
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end case;
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end case;
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|
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| Line 136... |
Line 138... |
|
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-- Process that handles the execution of each instruction
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-- Process that handles the execution of each instruction
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process (currentExState)
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process (currentExState)
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--variable operando1_reg : std_logic_vector(generalRegisters'range);
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--variable operando1_reg : std_logic_vector(generalRegisters'range);
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variable opcodeIR : std_logic_vector(5 downto 0);
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variable opcodeIR : std_logic_vector(5 downto 0);
|
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variable operand_reg1 : std_logic_vector(3 downto 0);
|
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variable operand_reg2 : std_logic_vector(3 downto 0);
|
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variable operand_imm : std_logic_vector(21 downto 0);
|
begin
|
begin
|
opcodeIR := IR((IR'HIGH) downto (IR'HIGH - 5));
|
-- Parse the common operands
|
|
opcodeIR := IR((IR'HIGH) downto (IR'HIGH - 5)); -- 6 Bits opcode (Max 64 instructions)
|
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operand_reg1 := IR((IR'HIGH - 6) downto (IR'HIGH - 9)); -- 4 bits register operand1 (Max 16 registers)
|
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operand_reg2 := IR((IR'HIGH - 10) downto (IR'HIGH - 13)); -- 4 bits register operand2 (Max 16 registers
|
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operand_imm := IR((IR'HIGH - 10) downto (IR'LOW)); -- 22 bits imediate value (Max value 4194304)
|
|
|
|
-- Select the instruction and init it's execution
|
case currentExState is
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case currentExState is
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when s0 =>
|
when initInstructionExecution =>
|
case opcodeIR is
|
case opcodeIR is
|
|
-- MOV r2,r1 (See the testDatapath to see how to drive the datapath for this function)
|
when mov_reg =>
|
when mov_reg =>
|
null;
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MuxDp <= muxPos(fromRegFileB);
|
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DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg2)));
|
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DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
|
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DpRegFileReadEnB <= '1';
|
|
nextExState <= writeRegister;
|
|
|
|
-- ADD r2,r0 (See the testDatapath to see how to drive the datapath for this function)
|
|
when add_reg | sub_reg | and_reg | or_reg | xor_reg =>
|
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MuxDp <= muxPos(fromAlu);
|
|
MuxRegDp <= muxRegPos(fromRegFileA);
|
|
DpRegFileReadAddrA <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Read first operand
|
|
DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg2))); -- Read second operand
|
|
DpRegFileReadEnA <= '1';
|
|
DpRegFileReadEnB <= '1';
|
|
DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Point to write in first operand (pointing to register)
|
|
DpAluOp <= opcode2AluOp(opcodeIR); -- Select the alu operation from the operand
|
|
nextExState <= writeRegister;
|
|
|
|
-- MOV r0,10d (See the testDatapath to see how to drive the datapath for this function)
|
|
when mov_val =>
|
|
MuxDp <= muxPos(fromImediate);
|
|
DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
|
|
ImmDp <= "0000000000" & operand_imm; -- & is used to concatenate signals
|
|
nextExState <= writeRegister;
|
|
|
|
-- ADD r3,2 (r2 <= r2+2) (See the testDatapath to see how to drive the datapath for this function)
|
|
when add_val | sub_val | and_val | or_val | xor_val =>
|
|
MuxDp <= muxPos(fromAlu);
|
|
MuxRegDp <= muxRegPos(fromImediate);
|
|
DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
|
|
DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Read first operand
|
|
DpRegFileReadEnB <= '1';
|
|
ImmDp <= "0000000000" & operand_imm; -- & is used to concatenate signals
|
|
DpAluOp <= opcode2AluOp(opcodeIR); -- Select the alu operation from the operand
|
|
nextExState <= writeRegister;
|
|
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
|
|
|
-- Write something on the register files
|
|
when writeRegister =>
|
|
DpRegFileWriteEn <= '1';
|
|
nextExState <= releaseWriteRead;
|
|
|
|
-- Release lines (Reset Datapath lines to something that does nothing...)
|
|
when releaseWriteRead =>
|
|
DpRegFileReadEnB <= '0';
|
|
DpRegFileReadEnA <= '0';
|
|
DpRegFileWriteEn <= '0';
|
|
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
