| Line 20... |
Line 20... |
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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Port ( reset : in STD_LOGIC;
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Port ( reset : in STD_LOGIC;
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clk : in STD_LOGIC; --! Main system clock
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clk : in STD_LOGIC; --! Main system clock
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FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
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FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
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DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
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DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
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outEnDp : out typeEnDis; --! Enable/Disable datapath output
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MuxDp : out STD_LOGIC_VECTOR (2 downto 0); --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
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MuxDp : out STD_LOGIC_VECTOR (2 downto 0); --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
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MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
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MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
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ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
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ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
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DpAluOp : out aluOps; --! Alu operations
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DpAluOp : out aluOps; --! Alu operations
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DpRegFileWriteAddr : out generalRegisters; --! General register address to write
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DpRegFileWriteAddr : out generalRegisters; --! General register address to write
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| Line 111... |
Line 112... |
MemoryDataReadEn <= '0';
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MemoryDataReadEn <= '0';
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MemoryDataWriteEn <= '0';
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MemoryDataWriteEn <= '0';
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|
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-- The high attribute points to the highes bit position
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-- The high attribute points to the highes bit position
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case opcodeIR is
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case opcodeIR is
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when mov_reg | mov_val | add_reg | sub_reg | and_reg | or_reg | xor_reg =>
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when mov_reg | mov_val | add_reg | sub_reg | and_reg | or_reg | xor_reg | ld_reg | ld_val | stom_reg | stom_val =>
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nextCpuState <= execute;
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nextCpuState <= execute;
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cyclesExecute := 3; -- Wait 3 cycles for mov operation
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cyclesExecute := 3; -- Wait 3 cycles for mov operation
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currInstruction <= IR;
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currInstruction <= IR;
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|
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when jmp_val | jmpr_val =>
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when jmp_val | jmpr_val =>
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| Line 129... |
Line 130... |
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-- Wait while the process that handles the execution works..
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-- Wait while the process that handles the execution works..
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when execute =>
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when execute =>
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-- On the case of jump instructions, it's execution will be handled on this process
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-- On the case of jump instructions, it's execution will be handled on this process
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case opcodeIR is
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case opcodeIR is
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|
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when jmp_val =>
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when jmp_val =>
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PC <= "0000000000" & operand_imm;
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PC <= "0000000000" & operand_imm;
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|
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when jmpr_val =>
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when jmpr_val =>
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PC <= PC + ("0000000000" & operand_imm);
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PC <= PC + ("0000000000" & operand_imm);
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|
|
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when ld_val =>
|
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MemoryDataRdAddr <= "0000000000" & operand_imm;
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MemoryDataReadEn <= '1';
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|
|
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-- STORE r1,10 (Store the value on r1 in the main memory located at address 10)
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when stom_val =>
|
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MemoryDataWrAddr <= "0000000000" & operand_imm;
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MemoryDataWriteEn <= '1';
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MemoryDataOut <= DataDp;
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|
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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|
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if cyclesExecute = 0 then
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if cyclesExecute = 0 then
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| Line 154... |
Line 168... |
when others =>
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when others =>
|
null;
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null;
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end case;
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end case;
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end process;
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end process;
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|
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-- Process that handles the execution of each instruction (Excluding the call and jump instructions)
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-- Process that handles the execution of each instruction (Excluding the call,jump,load,store instructions)
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process (currentExState)
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process (currentExState)
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--variable operando1_reg : std_logic_vector(generalRegisters'range);
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--variable operando1_reg : std_logic_vector(generalRegisters'range);
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variable opcodeIR : std_logic_vector(5 downto 0);
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variable opcodeIR : std_logic_vector(5 downto 0);
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variable operand_reg1 : std_logic_vector(3 downto 0);
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variable operand_reg1 : std_logic_vector(3 downto 0);
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variable operand_reg2 : std_logic_vector(3 downto 0);
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variable operand_reg2 : std_logic_vector(3 downto 0);
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| Line 180... |
Line 194... |
DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg2)));
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DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg2)));
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DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
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DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
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DpRegFileReadEnB <= '1';
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DpRegFileReadEnB <= '1';
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nextExState <= writeRegister;
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nextExState <= writeRegister;
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|
|
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-- LOAD r1,10 (Load into r1, the value in the main memory located at address 10)
|
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when ld_val =>
|
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MuxDp <= muxPos(fromMemory);
|
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DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
|
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-- The part that interface with the memory is located on the first process
|
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nextExState <= writeRegister;
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|
|
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-- STORE r1,10 (Store the value on r1 in the main memory located at address 10)
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|
when stom_val =>
|
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MuxDp <= muxPos(fromRegFileB);
|
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DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
|
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DpRegFileReadEnB <= '1';
|
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nextExState <= readRegisterB;
|
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-- The part that interface with the memory is located on the first process
|
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nextExState <= readRegisterB;
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|
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-- ADD r2,r0 (See the testDatapath to see how to drive the datapath for this function)
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-- ADD r2,r0 (See the testDatapath to see how to drive the datapath for this function)
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when add_reg | sub_reg | and_reg | or_reg | xor_reg =>
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when add_reg | sub_reg | and_reg | or_reg | xor_reg =>
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MuxDp <= muxPos(fromAlu);
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MuxDp <= muxPos(fromAlu);
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MuxRegDp <= muxRegPos(fromRegFileA);
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MuxRegDp <= muxRegPos(fromRegFileA);
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DpRegFileReadAddrA <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Read first operand
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DpRegFileReadAddrA <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Read first operand
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| Line 219... |
Line 249... |
-- Write something on the register files
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-- Write something on the register files
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when writeRegister =>
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when writeRegister =>
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DpRegFileWriteEn <= '1';
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DpRegFileWriteEn <= '1';
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nextExState <= releaseWriteRead;
|
nextExState <= releaseWriteRead;
|
|
|
|
when readRegisterB =>
|
|
DpRegFileReadEnB <= '1';
|
|
outEnDp <= enable;
|
|
nextExState <= releaseWriteRead;
|
|
|
|
when readRegisterA =>
|
|
DpRegFileReadEnA <= '1';
|
|
outEnDp <= enable;
|
|
nextExState <= releaseWriteRead;
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|
|
-- Release lines (Reset Datapath lines to something that does nothing...)
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-- Release lines (Reset Datapath lines to something that does nothing...)
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when releaseWriteRead =>
|
when releaseWriteRead =>
|
DpRegFileReadEnB <= '0';
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DpRegFileReadEnB <= '0';
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DpRegFileReadEnA <= '0';
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DpRegFileReadEnA <= '0';
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DpRegFileWriteEn <= '0';
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DpRegFileWriteEn <= '0';
|
|
outEnDp <= disable;
|
|
|
when others =>
|
when others =>
|
null;
|
null;
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end case;
|
end case;
|
end process;
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end process;
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