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clk : in STD_LOGIC; --! Main system clock
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clk : in STD_LOGIC; --! Main system clock
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FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
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FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
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DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
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DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
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outEnDp : out typeEnDis; --! Enable/Disable datapath output
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outEnDp : out typeEnDis; --! Enable/Disable datapath output
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MuxDp : out dpMuxInputs; --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
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MuxDp : out dpMuxInputs; --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
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MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
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MuxRegDp : out dpMuxAluIn; --! Select Alu InputA (Memory,Imediate,RegFileA)
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ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
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ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
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DpAluOp : out aluOps; --! Alu operations
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DpAluOp : out aluOps; --! Alu operations
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DpRegFileWriteAddr : out generalRegisters; --! General register address to write
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DpRegFileWriteAddr : out generalRegisters; --! General register address to write
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DpRegFileWriteEn : out STD_LOGIC; --! Enable register write
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DpRegFileWriteEn : out STD_LOGIC; --! Enable register write
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DpRegFileReadAddrA : out generalRegisters; --! General register address to read
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DpRegFileReadAddrA : out generalRegisters; --! General register address to read
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nextExState <= readRegisterB;
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nextExState <= readRegisterB;
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-- ADD r2,r0 (See the testDatapath to see how to drive the datapath for this function)
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-- ADD r2,r0 (See the testDatapath to see how to drive the datapath for this function)
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when add_reg | sub_reg | and_reg | or_reg | xor_reg =>
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when add_reg | sub_reg | and_reg | or_reg | xor_reg =>
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MuxDp <= fromAlu;
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MuxDp <= fromAlu;
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MuxRegDp <= muxRegPos(fromRegFileA);
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MuxRegDp <= fromRegFileA;
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DpRegFileReadAddrA <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Read first operand
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DpRegFileReadAddrA <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Read first operand
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DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg2))); -- Read second operand
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DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg2))); -- Read second operand
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DpRegFileReadEnA <= '1';
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DpRegFileReadEnA <= '1';
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DpRegFileReadEnB <= '1';
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DpRegFileReadEnB <= '1';
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DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Point to write in first operand (pointing to register)
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DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Point to write in first operand (pointing to register)
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nextExState <= writeRegister;
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nextExState <= writeRegister;
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-- ADD r3,2 (r2 <= r2+2) (See the testDatapath to see how to drive the datapath for this function)
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-- ADD r3,2 (r2 <= r2+2) (See the testDatapath to see how to drive the datapath for this function)
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when add_val | sub_val | and_val | or_val | xor_val =>
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when add_val | sub_val | and_val | or_val | xor_val =>
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MuxDp <= fromAlu;
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MuxDp <= fromAlu;
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MuxRegDp <= muxRegPos(fromImediate);
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MuxRegDp <= fromImediate;
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DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
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DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
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DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Read first operand
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DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Read first operand
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DpRegFileReadEnB <= '1';
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DpRegFileReadEnB <= '1';
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ImmDp <= "0000000000" & operand_imm; -- & is used to concatenate signals
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ImmDp <= "0000000000" & operand_imm; -- & is used to concatenate signals
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DpAluOp <= opcode2AluOp(opcodeIR); -- Select the alu operation from the operand
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DpAluOp <= opcode2AluOp(opcodeIR); -- Select the alu operation from the operand
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