| Line 21... |
Line 21... |
inputImm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from imediate value (instructions...)
|
inputImm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from imediate value (instructions...)
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clk : in STD_LOGIC; --! Clock signal
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clk : in STD_LOGIC; --! Clock signal
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outEn : in typeEnDis; --! Enable/Disable datapath output
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outEn : in typeEnDis; --! Enable/Disable datapath output
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aluOp : in aluOps; --! Alu operations
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aluOp : in aluOps; --! Alu operations
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muxSel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
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muxSel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
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muxRegFile : in STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
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regFileWriteAddr : in generalRegisters; --! General register write address
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regFileWriteAddr : in generalRegisters; --! General register write address
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regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
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regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
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regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
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regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
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regFileReadAddrB : in generalRegisters; --! General register read address (PortB)
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regFileReadAddrB : in generalRegisters; --! General register read address (PortB)
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regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
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regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
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| Line 47... |
Line 48... |
E : in STD_LOGIC_VECTOR (n downto 0); --! Fifth Input
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E : in STD_LOGIC_VECTOR (n downto 0); --! Fifth Input
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sel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs (1, 2, 3, 4, 5)
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sel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs (1, 2, 3, 4, 5)
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S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
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S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
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END COMPONENT;
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END COMPONENT;
|
|
|
|
--! Component declaration to instantiate the Multiplexer3_1 circuit
|
|
COMPONENT Multiplexer3_1 is
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|
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
|
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
|
|
B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
|
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C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
|
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sel : in STD_LOGIC_VECTOR(1 downto 0); --! Select inputs (1, 2, 3)
|
|
S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
|
|
end COMPONENT;
|
|
|
--! Component declaration to instantiate the Alu circuit
|
--! Component declaration to instantiate the Alu circuit
|
COMPONENT Alu
|
COMPONENT Alu
|
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
|
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
|
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 1
|
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 1
|
B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2
|
B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2
|
| Line 85... |
Line 96... |
-- Signals that will connect the various components from the DataPath
|
-- Signals that will connect the various components from the DataPath
|
signal regFilePortA : STD_LOGIC_VECTOR (n downto 0);
|
signal regFilePortA : STD_LOGIC_VECTOR (n downto 0);
|
signal regFilePortB : STD_LOGIC_VECTOR (n downto 0);
|
signal regFilePortB : STD_LOGIC_VECTOR (n downto 0);
|
signal aluOut : STD_LOGIC_VECTOR (n downto 0);
|
signal aluOut : STD_LOGIC_VECTOR (n downto 0);
|
signal muxOut : STD_LOGIC_VECTOR (n downto 0);
|
signal muxOut : STD_LOGIC_VECTOR (n downto 0);
|
|
signal muxOutReg : STD_LOGIC_VECTOR (n downto 0);
|
begin
|
begin
|
--! Instantiate Multiplexer
|
--! Instantiate Multiplexer 5:1
|
uMux: Multiplexer4_1 PORT MAP (
|
uMux: Multiplexer4_1 PORT MAP (
|
A => inputMm,
|
A => inputMm,
|
B => inputImm,
|
B => inputImm,
|
C => regFilePortA,
|
C => regFilePortA,
|
D => regFilePortB,
|
D => regFilePortB,
|
E => aluOut,
|
E => aluOut,
|
sel => muxSel,
|
sel => muxSel,
|
S => muxOut
|
S => muxOut
|
);
|
);
|
|
|
|
--! Instantiate Multiplexer 5:1
|
|
uMux2: Multiplexer3_1 PORT MAP (
|
|
A => inputMm,
|
|
B => inputImm,
|
|
C => regFilePortA,
|
|
sel => muxRegFile,
|
|
S => muxOutReg
|
|
);
|
|
|
--! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
|
--! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
|
uAlu: Alu PORT MAP (
|
uAlu: Alu PORT MAP (
|
A => regFilePortA,
|
A => muxOutReg,
|
B => regFilePortB,
|
B => regFilePortB,
|
S => aluOut,
|
S => aluOut,
|
sel => aluOp
|
sel => aluOp
|
);
|
);
|
|
|
