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[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [Multiplexer3_1.vhd] - Diff between revs 27 and 47
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Rev 47 |
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entity Multiplexer3_1 is
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entity Multiplexer3_1 is
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
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B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
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B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
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C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
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C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
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sel : in STD_LOGIC_VECTOR(1 downto 0); --! Select inputs (1, 2, 3)
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sel : in dpMuxAluIn; --! Select inputs (fromMemory, fromImediate, fromRegFileA)
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S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
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S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
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end Multiplexer3_1;
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end Multiplexer3_1;
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--! @brief Architure definition of the MUX
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--! @brief Architure definition of the MUX
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--! @details On this case we're going to use VHDL combinational description
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--! @details On this case we're going to use VHDL combinational description
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architecture Behavioral of Multiplexer3_1 is
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architecture Behavioral of Multiplexer3_1 is
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begin
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begin
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with sel select
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with sel select
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S <= A when "00",
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S <= A when fromMemory,
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B when "01",
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B when fromImediate,
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C when "10",
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C when fromRegFileA,
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(others => 'Z') when others;
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(others => 'Z') when others;
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end Behavioral;
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end Behavioral;
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