URL
https://opencores.org/ocsvn/opencpu32/opencpu32/trunk
[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [Multiplexer3_1.vhd] - Diff between revs 27 and 47
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 27 |
Rev 47 |
| Line 15... |
Line 15... |
entity Multiplexer3_1 is
|
entity Multiplexer3_1 is
|
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
|
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
|
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
|
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
|
B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
|
B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
|
C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
|
C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
|
sel : in STD_LOGIC_VECTOR(1 downto 0); --! Select inputs (1, 2, 3)
|
sel : in dpMuxAluIn; --! Select inputs (fromMemory, fromImediate, fromRegFileA)
|
S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
|
S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
|
end Multiplexer3_1;
|
end Multiplexer3_1;
|
|
|
--! @brief Architure definition of the MUX
|
--! @brief Architure definition of the MUX
|
--! @details On this case we're going to use VHDL combinational description
|
--! @details On this case we're going to use VHDL combinational description
|
architecture Behavioral of Multiplexer3_1 is
|
architecture Behavioral of Multiplexer3_1 is
|
|
|
begin
|
begin
|
with sel select
|
with sel select
|
S <= A when "00",
|
S <= A when fromMemory,
|
B when "01",
|
B when fromImediate,
|
C when "10",
|
C when fromRegFileA,
|
(others => 'Z') when others;
|
(others => 'Z') when others;
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.