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--! Use standard library
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--! Use standard library
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library ieee;
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library ieee;
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use ieee.STD_LOGIC_1164.all;
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use ieee.STD_LOGIC_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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package pkgOpenCPU32 is
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package pkgOpenCPU32 is
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--! Declare constants, enums, functions used by the design
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--! Declare constants, enums, functions used by the design
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constant nBits : integer := 32;
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constant nBits : integer := 32;
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constant instructionSize : integer := nBits;
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constant instructionSize : integer := nBits;
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--! Number of general registers (r0..r15)
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--! Number of general registers (r0..r15)
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constant numGenRegs : integer := 16;
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constant numGenRegs : integer := 16;
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type aluOps is (alu_pass, alu_passB, alu_sum, alu_sub, alu_inc, alu_dec, alu_mul, alu_or, alu_and,
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type aluOps is (alu_pass, alu_passB, alu_sum, alu_sub, alu_inc, alu_dec, alu_mul, alu_udiv, alu_or, alu_and,
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alu_xor, alu_not, alu_shfLt, alu_shfRt, alu_roLt, alu_roRt);
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alu_xor, alu_not, alu_shfLt, alu_shfRt, alu_roLt, alu_roRt);
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type typeEnDis is (enable, disable);
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type typeEnDis is (enable, disable);
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type generalRegisters is (r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15);
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type generalRegisters is (r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15);
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type dpMuxInputs is (fromMemory, fromImediate, fromRegFileA, fromRegFileB, fromAlu);
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type dpMuxInputs is (fromMemory, fromImediate, fromRegFileA, fromRegFileB, fromAlu);
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type dpMuxAluIn is (fromMemory, fromImediate, fromRegFileA);
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type dpMuxAluIn is (fromMemory, fromImediate, fromRegFileA);
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function reg2Num (a: generalRegisters) return integer;
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function reg2Num (a: generalRegisters) return integer;
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function Num2reg (a: integer) return generalRegisters;
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function Num2reg (a: integer) return generalRegisters;
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function muxPos( a: dpMuxInputs) return std_logic_vector;
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function muxPos( a: dpMuxInputs) return std_logic_vector;
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function muxRegPos(a: dpMuxAluIn) return std_logic_vector;
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function muxRegPos(a: dpMuxAluIn) return std_logic_vector;
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function opcode2AluOp (opcode : std_logic_vector(5 downto 0)) return aluOps;
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function opcode2AluOp (opcode : std_logic_vector(5 downto 0)) return aluOps;
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function udivision(dividend: unsigned; divisor: unsigned) return unsigned;
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-- Opcodes
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-- Opcodes
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subtype opcodes is std_logic_vector(5 downto 0); -- 6 Bits (64 instructions max)
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subtype opcodes is std_logic_vector(5 downto 0); -- 6 Bits (64 instructions max)
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-- Each instruction will take 32 bits
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-- Each instruction will take 32 bits
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when others => valRet := alu_pass;
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when others => valRet := alu_pass;
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end case;
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end case;
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return valRet;
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return valRet;
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end opcode2AluOp;
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end opcode2AluOp;
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-- Code based on Restoring division algorithm
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-- http://vhdlguru.blogspot.com.br/2010/03/vhdl-function-for-division-two-signed.html
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-- http://en.wikipedia.org/wiki/Division_%28digital%29
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function udivision(dividend: unsigned; divisor: unsigned) return unsigned is
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variable a1 : unsigned(dividend'length-1 downto 0);
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variable b1 : unsigned(divisor'length-1 downto 0);
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variable p1 : unsigned(divisor'length downto 0);
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variable i : integer;
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begin
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a1 := dividend;
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b1 := divisor;
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p1 := (others => '0');
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i := 0;
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for i in 0 to divisor'length-1 loop
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p1(divisor'length-1 downto 1) := p1(divisor'length-2 downto 0);
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p1(0) := a1(dividend'length-1);
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a1(dividend'length-1 downto 1) := a1(dividend'length-2 downto 0);
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p1 := p1-b1;
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if(p1(divisor'length-1) ='1') then
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a1(0) :='0';
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p1 := p1+b1;
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else
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a1(0) :='1';
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end if;
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end loop;
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return a1;
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end;
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end pkgOpenCPU32;
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end pkgOpenCPU32;
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