URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [testAlu.vhd] - Diff between revs 9 and 12

Rev 9	Rev 12
Line 28...	Line 28...
`sel : in aluOps); --! Select operation`	`sel : in aluOps); --! Select operation`
`END COMPONENT;`	`END COMPONENT;`


`--Inputs`	`--Inputs`
`signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0');`	`signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component`
`signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0');`	`signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component`
`signal sel : aluOps := alu_sum;`	`signal sel : aluOps := alu_sum; --! Wire to connect Test signal to component`

`--Outputs`	`--Outputs`
`signal S : std_logic_vector((nBits - 1) downto 0);`	`signal S : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component`

`BEGIN`	`BEGIN`

`-- Instantiate the Unit Under Test (UUT)`	`--! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)`
`uut: Alu PORT MAP (`	`uut: Alu PORT MAP (`
`A => A,`	`A => A,`
`B => B,`	`B => B,`
`S => S,`	`S => S,`
`sel => sel`	`sel => sel`