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[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [testAlu.vhd] - Diff between revs 17 and 18

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Rev 17 Rev 18
Line 137... Line 137...
                A <= conv_std_logic_vector(10, nBits);
                A <= conv_std_logic_vector(10, nBits);
                B <= (others => 'X');
                B <= (others => 'X');
                wait for 1 ns;  -- Wait to stabilize the response
                wait for 1 ns;  -- Wait to stabilize the response
                assert S = (not A) report "Invalid NOT output" severity FAILURE;
                assert S = (not A) report "Invalid NOT output" severity FAILURE;
 
 
      wait;
      -- Finish simulation
 
                assert false report "NONE. End of simulation." severity failure;
   end process;
   end process;
 
 
END;
END;
 
 
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