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COMPONENT Alu
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COMPONENT Alu
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 1
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 1
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B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2
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B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2
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S : out STD_LOGIC_VECTOR (n downto 0); --! Alu Output
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S : out STD_LOGIC_VECTOR (n downto 0); --! Alu Output
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sel : in aluOps); --! Select operation
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flagsOut : out STD_LOGIC_VECTOR(2 downto 0); --! Flags from current operation
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sel : in aluOps); --! Select operation --! Select operation
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal sel : aluOps := alu_sum; --! Wire to connect Test signal to component
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signal sel : aluOps := alu_sum; --! Wire to connect Test signal to component
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--Outputs
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--Outputs
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signal S : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component
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signal S : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component
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signal flagsOut : std_logic_vector(2 downto 0); --! Wire to connect Test signal to component
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BEGIN
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BEGIN
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--! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
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--! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
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uut: Alu PORT MAP (
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uut: Alu PORT MAP (
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A => A,
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A => A,
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B => B,
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B => B,
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S => S,
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S => S,
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flagsOut => flagsOut,
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sel => sel
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sel => sel
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);
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);
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--! Process that will stimulate all of the Alu operations
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--! Process that will stimulate all of the Alu operations
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stim_proc: process
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stim_proc: process
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A <= conv_std_logic_vector(10, nBits);
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A <= conv_std_logic_vector(10, nBits);
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B <= (others => 'X');
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B <= (others => 'X');
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wait for 1 ns; -- Wait to stabilize the response
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wait for 1 ns; -- Wait to stabilize the response
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assert S = (not A) report "Invalid NOT output" severity FAILURE;
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assert S = (not A) report "Invalid NOT output" severity FAILURE;
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-- Shift left---------------------------------------------------------------------
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wait for 1 ns;
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REPORT "Shift left 2" SEVERITY NOTE;
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sel <= alu_shfLt;
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A <= conv_std_logic_vector(2, nBits);
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B <= (others => 'X');
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wait for 1 ns; -- Wait to stabilize the response
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assert S = conv_std_logic_vector(4, nBits) report "Invalid shift left output expected " severity FAILURE;
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-- Shift right---------------------------------------------------------------------
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wait for 1 ns;
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REPORT "Shift right 4" SEVERITY NOTE;
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sel <= alu_shfRt;
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A <= conv_std_logic_vector(4, nBits);
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B <= (others => 'X');
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wait for 1 ns; -- Wait to stabilize the response
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assert S = conv_std_logic_vector(2, nBits) report "Invalid shift left output expected " severity FAILURE;
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-- Test flag zero ------------------------------------------------------------------
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wait for 1 ps;
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REPORT "Test zero flag 10 sub 10" SEVERITY NOTE;
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sel <= alu_sub;
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A <= conv_std_logic_vector(10, nBits);
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B <= conv_std_logic_vector(10, nBits);
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wait for 1 ns; -- Wait to stabilize the response
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assert flagsOut(flag_zero) = '1' report "Invalid zero flag" severity FAILURE;
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-- Test flag carry ------------------------------------------------------------------
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wait for 1 ps;
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REPORT "Test carry flag 4294967056 sum 4294967056" SEVERITY NOTE;
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sel <= alu_sum;
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A <= "11111111111111111111111100010000";
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B <= "11111111111111111111111100010000";
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wait for 1 ns; -- Wait to stabilize the response
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assert flagsOut(flag_carry) = '1' report "Invalid carry flag" severity FAILURE;
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-- Test flag sign ------------------------------------------------------------------
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wait for 1 ps;
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REPORT "Test sign flag -4 sub 4" SEVERITY NOTE;
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sel <= alu_sub;
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A <= conv_std_logic_vector(-4, nBits);
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B <= conv_std_logic_vector(4, nBits);
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wait for 1 ns; -- Wait to stabilize the response
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assert flagsOut(flag_sign) = '1' report "Invalid sign flag" severity FAILURE;
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assert S = conv_std_logic_vector(-8, nBits) report "Invalid Sub" severity FAILURE;
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-- Finish simulation
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-- Finish simulation
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assert false report "NONE. End of simulation." severity failure;
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assert false report "NONE. End of simulation." severity failure;
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end process;
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end process;
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END;
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END;
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