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[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [testAlu.vhd] - Diff between revs 18 and 28

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Rev 18 Rev 28
Line 23... Line 23...
    COMPONENT Alu
    COMPONENT Alu
    generic (n : integer := nBits - 1);                                 --! Generic value (Used to easily change the size of the Alu on the package)
    generic (n : integer := nBits - 1);                                 --! Generic value (Used to easily change the size of the Alu on the package)
         Port ( A : in  STD_LOGIC_VECTOR (n downto 0);           --! Alu Operand 1
         Port ( A : in  STD_LOGIC_VECTOR (n downto 0);           --! Alu Operand 1
           B : in  STD_LOGIC_VECTOR (n downto 0);                --! Alu Operand 2
           B : in  STD_LOGIC_VECTOR (n downto 0);                --! Alu Operand 2
           S : out  STD_LOGIC_VECTOR (n downto 0);               --! Alu Output
           S : out  STD_LOGIC_VECTOR (n downto 0);               --! Alu Output
           sel : in  aluOps);                                                                   --! Select operation
                          flagsOut : out STD_LOGIC_VECTOR(2 downto 0);   --! Flags from current operation
 
           sel : in  aluOps);                                                                           --! Select operation                                                            --! Select operation
    END COMPONENT;
    END COMPONENT;
 
 
 
 
   --Inputs
   --Inputs
   signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0');  --! Wire to connect Test signal to component
   signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0');  --! Wire to connect Test signal to component
   signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0');  --! Wire to connect Test signal to component
   signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0');  --! Wire to connect Test signal to component
   signal sel : aluOps := alu_sum;                                                                                                              --! Wire to connect Test signal to component
   signal sel : aluOps := alu_sum;                                                                                                              --! Wire to connect Test signal to component
 
 
        --Outputs
        --Outputs
   signal S : std_logic_vector((nBits - 1) downto 0);                                                            --! Wire to connect Test signal to component
   signal S : std_logic_vector((nBits - 1) downto 0);                                                            --! Wire to connect Test signal to component
 
        signal flagsOut : std_logic_vector(2 downto 0);                                                                  --! Wire to connect Test signal to component
 
 
BEGIN
BEGIN
 
 
        --! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
        --! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
   uut: Alu PORT MAP (
   uut: Alu PORT MAP (
          A => A,
          A => A,
          B => B,
          B => B,
          S => S,
          S => S,
 
                         flagsOut => flagsOut,
          sel => sel
          sel => sel
        );
        );
 
 
   --! Process that will stimulate all of the Alu operations
   --! Process that will stimulate all of the Alu operations
   stim_proc: process
   stim_proc: process
Line 137... Line 140...
                A <= conv_std_logic_vector(10, nBits);
                A <= conv_std_logic_vector(10, nBits);
                B <= (others => 'X');
                B <= (others => 'X');
                wait for 1 ns;  -- Wait to stabilize the response
                wait for 1 ns;  -- Wait to stabilize the response
                assert S = (not A) report "Invalid NOT output" severity FAILURE;
                assert S = (not A) report "Invalid NOT output" severity FAILURE;
 
 
 
                -- Shift left---------------------------------------------------------------------
 
                wait for 1 ns;
 
                REPORT "Shift left 2" SEVERITY NOTE;
 
                sel <= alu_shfLt;
 
                A <= conv_std_logic_vector(2, nBits);
 
                B <= (others => 'X');
 
                wait for 1 ns;  -- Wait to stabilize the response
 
                assert S = conv_std_logic_vector(4, nBits) report "Invalid shift left output expected " severity FAILURE;
 
 
 
                -- Shift right---------------------------------------------------------------------
 
                wait for 1 ns;
 
                REPORT "Shift right 4" SEVERITY NOTE;
 
                sel <= alu_shfRt;
 
                A <= conv_std_logic_vector(4, nBits);
 
                B <= (others => 'X');
 
                wait for 1 ns;  -- Wait to stabilize the response
 
                assert S = conv_std_logic_vector(2, nBits) report "Invalid shift left output expected " severity FAILURE;
 
 
 
                -- Test flag zero ------------------------------------------------------------------
 
                wait for 1 ps;
 
                REPORT "Test zero flag 10 sub 10" SEVERITY NOTE;
 
                sel <= alu_sub;
 
                A <= conv_std_logic_vector(10, nBits);
 
                B <= conv_std_logic_vector(10, nBits);
 
                wait for 1 ns;  -- Wait to stabilize the response
 
                assert flagsOut(flag_zero) = '1' report "Invalid zero flag" severity FAILURE;
 
 
 
                -- Test flag carry ------------------------------------------------------------------
 
                wait for 1 ps;
 
                REPORT "Test carry flag 4294967056 sum 4294967056" SEVERITY NOTE;
 
                sel <= alu_sum;
 
                A <= "11111111111111111111111100010000";
 
                B <= "11111111111111111111111100010000";
 
                wait for 1 ns;  -- Wait to stabilize the response
 
                assert flagsOut(flag_carry) = '1' report "Invalid carry flag" severity FAILURE;
 
 
 
                -- Test flag sign ------------------------------------------------------------------
 
                wait for 1 ps;
 
                REPORT "Test sign flag -4 sub 4" SEVERITY NOTE;
 
                sel <= alu_sub;
 
                A <= conv_std_logic_vector(-4, nBits);
 
                B <= conv_std_logic_vector(4, nBits);
 
                wait for 1 ns;  -- Wait to stabilize the response
 
                assert flagsOut(flag_sign) = '1' report "Invalid sign flag" severity FAILURE;
 
                assert S = conv_std_logic_vector(-8, nBits) report "Invalid Sub" severity FAILURE;
 
 
      -- Finish simulation
      -- Finish simulation
                assert false report "NONE. End of simulation." severity failure;
                assert false report "NONE. End of simulation." severity failure;
   end process;
   end process;
 
 
END;
END;

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