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[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [testControlUnit.vhd] - Diff between revs 34 and 35

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Rev 34 Rev 35
Line 234... Line 234...
                assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
                assert outEnDp = disable report "Invalid value" severity FAILURE;
                assert outEnDp = disable report "Invalid value" severity FAILURE;
                -------------------------------------------------------------------------------------------------
                -------------------------------------------------------------------------------------------------
 
 
 
                -- ADD r2,2 (Compare control unit outputs with Datapath)--------------------------------------
 
                REPORT "ADD r2,2" SEVERITY NOTE;
 
                MemoryDataInput <= add_val & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(2, 22);
 
                wait for CLK_period;    -- Fetch
 
                wait for CLK_period;    -- Decode
 
                wait for CLK_period;    -- Execute
 
 
 
                -- Verify if signals for the datapath are valid         
 
                assert ImmDp = conv_std_logic_vector(2, nBits) report "Invalid value" severity FAILURE;
 
                assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
 
      assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
 
                assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;
 
                assert MuxRegDp = muxRegPos(fromImediate) report "Invalid value" severity FAILURE;
 
                assert DpRegFileReadAddrB = r2 report "Invalid value" severity FAILURE;
 
                assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
 
 
 
                wait for CLK_period;    -- Executing ... 1
 
 
 
                -- State writing on the registers
 
                assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;
 
 
 
                wait for CLK_period;    -- Executing ...2 (Releasing lines.... (Next instruction should come...)                                
 
 
 
                -- Verify if all lines are unasserted
 
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
 
                assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;
 
                assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
 
                assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
 
                assert outEnDp = disable report "Invalid value" severity FAILURE;
 
                -------------------------------------------------------------------------------------------------
 
 
      -- Finish simulation
      -- Finish simulation
                assert false report "NONE. End of simulation." severity failure;
                assert false report "NONE. End of simulation." severity failure;
                wait;
                wait;
   end process;
   end process;
 
 

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